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公开(公告)号：US20110296148A1
公开(公告)日：2011-12-01
申请号：US12788351
申请日：2010-05-27
申请人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
发明人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
IPC分类号： G06F9/312
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30189 , G06F9/3834 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F9/467
摘要： Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.
摘要翻译： 在具有处理器和事务存储器的数据处理系统中提供用于在数据处理系统中执行事务的机制。 这些机制执行包括修改事务存储器的至少一部分的一个或多个指令的事务。 响应于由处理器执行的事务挂起指令，事务被暂停。 当事务被暂停时，暂停的代码块以非事务方式执行。 确定在事务中止时是否发生中断。 响应于在事务中止时发生的中断，事务中止操作被延迟，直到事务中止停止为止。
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公开(公告)号：US08296547B2
公开(公告)日：2012-10-23
申请号：US12548213
申请日：2009-08-26
申请人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
发明人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/1009
摘要： An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.
摘要翻译： 一种用于通过间接TLB条目在硬件中将条目加载到翻译后备缓冲器（TLB）中的增强机制。 在一个实施例中，如果在TLB中没有找到与给定虚拟地址相关联的直接TLB条目，则检查TLB与给定虚拟地址相关联的间接TLB条目。 每个间接TLB条目提供与指定范围的虚拟地址相关联的页表的真实地址，并且包括页表条目数组。 如果在TLB中找到与给定虚拟地址相关联的间接TLB条目，则通过组合来自间接TLB条目的实际地址字段和来自给定虚拟地址的比特来产生计算的地址，获得页表条目（PTE） 通过从所计算的地址的存储器读取一个字，并且将PTE作为直接TLB条目加载到TLB中。
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3.发明申请公开(公告)号：US20110153955A1
公开(公告)日：2011-06-23
申请号：US12641766
申请日：2009-12-18
CPC分类号： G06F12/1018 , G06F12/1027 , G06F2212/652
摘要： A computer implemented method searches a unified translation lookaside buffer. Responsive to a request to access the unified translation lookaside buffer, a first order code within a first entry of a search priority configuration register is identified. A unified translation lookaside buffer is then searched according to the first order code for a hashed page entry. If the hashed page entry is not found when searching a unified translation lookaside buffer according to the first order code, a second order code is identified within a second entry of the search priority configuration register. The unified translation lookaside buffer is then searched according to the second order code for the hashed page entry.
摘要翻译： 计算机实现的方法搜索统一的翻译后备缓冲器。 响应于访问统一翻译后备缓冲器的请求，识别搜索优先级配置寄存器的第一条目内的第一订单代码。 然后根据散列页面条目的第一个订单代码搜索统一的翻译后备缓冲区。 如果在根据第一订单代码搜索统一的翻译后备缓冲器时找不到散列页条目，则在搜索优先级配置寄存器的第二条目内识别第二订单代码。 然后根据散列页面条目的二阶代码搜索统一的翻译后备缓冲区。
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4.发明申请METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES 失效用于管理翻译实体的不同级别的虚拟机的物理存储器访问的软件控制的缓存的方法和装置公开(公告)号：US20130007408A1
公开(公告)日：2013-01-03
申请号：US13616515
申请日：2012-09-14
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/4555 , G06F2212/651
摘要： A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
摘要翻译： 公开了一种允许客户操作系统（客户操作系统）直接修改TLB中的条目而不涉及管理程序的方法和系统。 客户操作系统在收到客户端TLB未命中异常时，向逻辑发出TLBWE（TLB写入条目）指令。 该逻辑在管理员模式下运行TLBWE指令，而不调用管理程序。 TLB可以包含访客页表中的条目和主页页表中的条目。
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5.发明授权Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities 有权用于管理在不同级别的翻译实体之间翻译虚拟机的物理存储器访问的软件控制缓存的方法和装置公开(公告)号：US08275971B2
公开(公告)日：2012-09-25
申请号：US12199381
申请日：2008-08-27
CPC分类号： G06F12/1027 , G06F9/4555 , G06F2212/651
摘要： A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
摘要翻译： 公开了一种允许客户操作系统（客户操作系统）直接修改TLB中的条目而不涉及管理程序的方法和系统。 客户操作系统在收到客户端TLB未命中异常时，向逻辑发出TLBWE（TLB写入条目）指令。 该逻辑在管理员模式下执行TLBWE指令，而不调用管理程序。 TLB可以包含访客页表中的条目和主页页表中的条目。
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公开(公告)号：US09626187B2
公开(公告)日：2017-04-18
申请号：US12788351
申请日：2010-05-27
申请人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
发明人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30189 , G06F9/3834 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F9/467
摘要： Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.
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公开(公告)号：US08364933B2
公开(公告)日：2013-01-29
申请号：US12641766
申请日：2009-12-18
IPC分类号： G06F12/10
CPC分类号： G06F12/1018 , G06F12/1027 , G06F2212/652
摘要： A computer implemented method searches a unified translation lookaside buffer. Responsive to a request to access the unified translation lookaside buffer, a first order code within a first entry of a search priority configuration register is identified. A unified translation lookaside buffer is then searched according to the first order code for a hashed page entry. If the hashed page entry is not found when searching a unified translation lookaside buffer according to the first order code, a second order code is identified within a second entry of the search priority configuration register. The unified translation lookaside buffer is then searched according to the second order code for the hashed page entry.
摘要翻译： 计算机实现的方法搜索统一的翻译后备缓冲器。 响应于访问统一翻译后备缓冲器的请求，识别搜索优先级配置寄存器的第一条目内的第一订单代码。 然后根据散列页面条目的第一个订单代码搜索统一的翻译后备缓冲区。 如果在根据第一订单代码搜索统一的翻译后备缓冲器时找不到散列页条目，则在搜索优先级配置寄存器的第二条目内识别第二订单代码。 然后根据散列页面条目的二阶代码搜索统一的翻译后备缓冲区。
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8.发明授权Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities 失效用于管理在不同级别的翻译实体之间翻译虚拟机的物理存储器访问的软件控制缓存的方法和装置公开(公告)号：US08688953B2
公开(公告)日：2014-04-01
申请号：US13616515
申请日：2012-09-14
CPC分类号： G06F12/1027 , G06F9/4555 , G06F2212/651
摘要： A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
摘要翻译： 公开了一种允许客户操作系统（客户操作系统）直接修改TLB中的条目而不涉及管理程序的方法和系统。 客户操作系统在收到客户端TLB未命中异常时，向逻辑发出TLBWE（TLB写入条目）指令。 该逻辑在管理员模式下运行TLBWE指令，而不调用管理程序。 TLB可以包含访客页表中的条目和主页页表中的条目。
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9.发明申请METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES 有权用于管理翻译实体的不同级别的虚拟机的物理存储器访问的软件控制的缓存的方法和装置公开(公告)号：US20100058358A1
公开(公告)日：2010-03-04
申请号：US12199381
申请日：2008-08-27
CPC分类号： G06F12/1027 , G06F9/4555 , G06F2212/651
摘要： A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
摘要翻译： 公开了一种允许客户操作系统（客户操作系统）直接修改TLB中的条目而不涉及管理程序的方法和系统。 客户操作系统在收到客户端TLB未命中异常时，向逻辑发出TLBWE（TLB写入条目）指令。 该逻辑在管理员模式下执行TLBWE指令，而不调用管理程序。 TLB可以包含访客页表中的条目和主页页表中的条目。
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公开(公告)号：US20100058026A1
公开(公告)日：2010-03-04
申请号：US12548213
申请日：2009-08-26
申请人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
发明人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
IPC分类号： G06F12/06
CPC分类号： G06F12/1027 , G06F12/1009
摘要： An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.
摘要翻译： 一种用于通过间接TLB条目在硬件中将条目加载到翻译后备缓冲器（TLB）中的增强机制。 在一个实施例中，如果在TLB中没有找到与给定虚拟地址相关联的直接TLB条目，则检查TLB与给定虚拟地址相关联的间接TLB条目。 每个间接TLB条目提供与指定范围的虚拟地址相关联的页表的真实地址，并且包括页表条目数组。 如果在TLB中找到与给定虚拟地址相关联的间接TLB条目，则通过组合来自间接TLB条目的实际地址字段和来自给定虚拟地址的比特来产生计算的地址，获得页表条目（PTE） 通过从所计算的地址的存储器读取一个字，并且将PTE作为直接TLB条目加载到TLB中。
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