公开(公告)号：US08300680B2

公开(公告)日：2012-10-30

申请号：US12615052

申请日：2009-11-09

申请人： Timothy Paul Pals ,  Soon-Seng Lau ,  Lennart K. Mathe

发明人： Timothy Paul Pals ,  Soon-Seng Lau ,  Lennart K. Mathe

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： H04B1/109 ,  H04B1/28

摘要： A method and apparatus for avoiding receiver interference is described herein. One or more potential interferers are determined and the frequency associated with the interferers is also determined A desired sampling frequency for the receiver is calculated to avoid the potential interferers.

摘要翻译： 本文描述了一种避免接收机干扰的方法和装置。 确定一个或多个潜在干扰源并且还确定与干扰源相关联的频率。为了避免潜在的干扰源，计算接收机的期望采样频率。

公开(公告)号：US20100316098A1

公开(公告)日：2010-12-16

申请号：US12615052

申请日：2009-11-09

申请人： Timothy Paul Pals ,  Soon-Seng Lau ,  Lennart K. Mathe

发明人： Timothy Paul Pals ,  Soon-Seng Lau ,  Lennart K. Mathe

IPC分类号： H04B1/38 ,  H04L27/06 ,  H04B1/10

CPC分类号： H04B1/109 ,  H04B1/28

摘要： A method and apparatus for avoiding receiver interference is described herein. One or more potential interferers are determined and the frequency associated with the interferers is also determined A desired sampling frequency for the receiver is calculated to avoid the potential interferers.

摘要翻译： 本文描述了一种避免接收机干扰的方法和装置。 确定一个或多个潜在干扰源并且还确定与干扰源相关联的频率。为了避免潜在的干扰源，计算接收机的期望采样频率。

公开(公告)号：US07898453B2

公开(公告)日：2011-03-01

申请号：US12329450

申请日：2008-12-05

申请人： Lennart K. Mathe

发明人： Lennart K. Mathe

IPC分类号： H03M1/12

CPC分类号： H03M1/462 ,  H03M1/466 ,  H03M1/804

摘要： A successive approximation analog-to-digital converter (ADC) includes a binary-weighted capacitor array, quantizer, and control block. One end of each capacitor is connected to the input of the quantizer, and a second end of each capacitor is controlled by the control block through a driver. A voltage is sampled, quantized, and stored as the most significant bit of the ADC's output. Depending on the result of the quantization, the control block toggles the driver of one of the capacitors corresponding to the most significant bit. The voltage at the common node is sampled again to obtain a second bit of the ADC's output. The operations are repeated as needed to obtain and store additional bits of the ADC's output. Similar configuration and process are described for a differential ADC. The operation is asynchronous, allowing extra time for metastable states only when such states occur.

摘要翻译： 逐次逼近模数转换器（ADC）包括二进制加权电容器阵列，量化器和控制块。 每个电容器的一端连接到量化器的输入，并且每个电容器的第二端由控制块通过驱动器控制。 电压被采样，量化并存储为ADC输出的最高有效位。 根据量化的结果，控制块切换对应于最高有效位的电容器之一的驱动器。 在公共节点处的电压被再次采样以获得ADC输出的第二位。 根据需要重复操作以获得并存储ADC输出的其他位。 差分ADC描述了类似的配置和过程。 该操作是异步的，只有当这种状态发生时才允许亚稳态的额外时间。

公开(公告)号：US20100244927A1

公开(公告)日：2010-09-30

申请号：US12494068

申请日：2009-06-29

申请人： Vladimir Aparin ,  Namsoo Kim ,  Lennart K. Mathe

发明人： Vladimir Aparin ,  Namsoo Kim ,  Lennart K. Mathe

IPC分类号： G06G7/12

CPC分类号： H04B1/525 ,  H03F1/34 ,  H03F3/24 ,  H04B1/0475 ,  H04B1/109 ,  H04B1/123 ,  H04B2001/0433

摘要： Exemplary embodiments of the invention disclose signal filtering. In an exemplary embodiment, a filter device may comprise a subtractor operably coupled between an input and an output and configured to receive an input signal comprising a desired component and at least one undesired frequency component. The filter device may further include a feedback loop configured to receive at least one of the input signal and an output signal from the subtractor and convey a feedback signal comprising at least one undesired component to the subtractor. Each undesired component of the feedback signal corresponds to an associated undesired component of the input signal. Furthermore, the subtractor subtracts the feedback signal from the input signal and convey the output signal

摘要翻译： 本发明的示例性实施例公开了信号滤波。 在示例性实施例中，滤波器装置可以包括可操作地耦合在输入端和输出端之间并被配置为接收包括期望分量和至少一个不需要的频率分量的输入信号的减法器。 滤波器装置还可以包括反馈回路，其被配置为从减法器接收输入信号和输出信号中的至少一个，并将包括至少一个不期望的分量的反馈信号传送到减法器。 反馈信号的每个不期望的分量对应于输入信号的相关不期望的分量。 此外，减法器从输入信号中减去反馈信号并传送输出信号

公开(公告)号：US20120326783A1

公开(公告)日：2012-12-27

申请号：US13167659

申请日：2011-06-23

申请人： Lennart K. Mathe ,  Thomas Domenick Marra ,  Todd R. Sutton

发明人： Lennart K. Mathe ,  Thomas Domenick Marra ,  Todd R. Sutton

IPC分类号： H03F3/217

CPC分类号： H03F1/0227 ,  H03F2200/102 ,  H03F2200/432 ,  H03F2200/462

摘要： Techniques for efficiently generating a power supply are described. In one design, an apparatus includes an envelope amplifier and a boost converter. The boost converter generates a boosted supply voltage having a higher voltage than a first supply voltage (e.g., a battery voltage). The envelope amplifier generates a second supply voltage based on an envelope signal and the boosted supply voltage (and also possibly the first supply voltage). A power amplifier operates based on the second supply voltage. In another design, an apparatus includes a switcher, an envelope amplifier, and a power amplifier. The switcher receives a first supply voltage and provides a first supply current. The envelope amplifier provides a second supply current based on an envelope signal. The power amplifier receives a total supply current including the first and second supply currents. In one design, the switcher detects the second supply current and adds an offset to generate a larger first supply current than without the offset.

摘要翻译： 描述用于有效地产生电源的技术。 在一种设计中，一种装置包括包络放大器和升压转换器。 升压转换器产生具有比第一电源电压（例如，电池电压）更高的电压的升压电源电压。 包络放大器基于包络信号和升高的电源电压（以及可能的第一电源电压）产生第二电源电压。 功率放大器基于第二电源电压进行工作。 在另一种设计中，装置包括切换器，包络放大器和功率放大器。 切换器接收第一电源电压并提供第一电源电流。 包络放大器基于包络信号提供第二电源电流。 功率放大器接收包括第一和第二电源电流的总电源电流。 在一种设计中，切换器检测第二电源电流，并增加偏移量以产生比没有偏移量更大的第一电源电流。

公开(公告)号：US08140026B2

公开(公告)日：2012-03-20

申请号：US12436288

申请日：2009-05-06

申请人： Xiaohong Quan ,  Lennart K. Mathe ,  Liang Dai ,  Dinesh J. Alladi

发明人： Xiaohong Quan ,  Lennart K. Mathe ,  Liang Dai ,  Dinesh J. Alladi

IPC分类号： H03K7/08 ,  H03K5/156

CPC分类号： H03K7/08 ,  H03K5/1565

摘要： All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

摘要翻译： 用于产生具有可选占空比的周期性数字信号的全数字技术。 在一个方面，提供了一个计算块，用于计算所选占空比与参考时钟周期与高频振荡周期之间的离散比的积。 计算块可以耦合到脉冲宽度发生器，用于产生具有作为高频振荡器周期的整数倍的脉冲宽度的信号。 另一方面，脉冲宽度发生器还可以通过对与高频振荡器的环形振荡器示例性实施例的各个反相器级匹配的延迟线的各个反相器级进行抽头来适应高频振荡器周期的混合分数倍。

公开(公告)号：US08144042B2

公开(公告)日：2012-03-27

申请号：US12486266

申请日：2009-06-17

申请人： Lennart K. Mathe

发明人： Lennart K. Mathe

IPC分类号： H03M3/00 ,  H03M1/66

CPC分类号： G06F17/5018 ,  G06F2217/84

摘要： A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate signals, which are used to generate output signals when the last input signal arrives. The combinatorial circuit includes an input calculation block, at least one pre-calculation block, and an output calculation block coupled in series. The input calculation block receives some input signals and generates intermediate signals for the first pre-calculation block. The pre-calculation block(s) receive at least one earlier input signal and generate additional intermediate signals. The output calculation block receives the latest input signal and the intermediate signals from the last pre-calculation block and generates the output signals. The pre-calculation block(s) and the output calculation block may be implemented with simple circuits. In another aspect, a delta sigma (ΔΣ) modulator may use the combinatorial circuit with pre-calculation in order to improve operating speed.

摘要翻译： 描述了具有预计算并具有较短延迟的组合电路。 组合电路使用早期输入信号可用的信息来预先计算中间信号，这些信号用于在最后一个输入信号到达时产生输出信号。 组合电路包括输入计算块，至少一个预计算块和串联耦合的输出计算块。 输入计算块接收一些输入信号并产生用于第一预计算块的中间信号。 预计算块接收至少一个较早的输入信号并产生附加的中间信号。 输出计算块从最后一个预计算块接收最新的输入信号和中间信号，并产生输出信号。 预计算块和输出计算块可以用简单的电路来实现。 另一方面，ΔΣ（＆Dgr＆amp; Sgr）调制器可以使用组合电路进行预先计算，以提高操作速度。

公开(公告)号：US20100283522A1

公开(公告)日：2010-11-11

申请号：US12436288

申请日：2009-05-06

申请人： Xiaohong Quan ,  Lennart K. Mathe ,  Liang Dai ,  Dinesh J. Alladi

发明人： Xiaohong Quan ,  Lennart K. Mathe ,  Liang Dai ,  Dinesh J. Alladi

IPC分类号： H03K3/017

CPC分类号： H03K7/08 ,  H03K5/1565

摘要： All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

摘要翻译： 用于产生具有可选占空比的周期性数字信号的全数字技术。 在一个方面，提供了一个计算块，用于计算所选占空比与参考时钟周期与高频振荡周期之间的离散比的积。 计算块可以耦合到脉冲宽度发生器，用于产生具有作为高频振荡器周期的整数倍的脉冲宽度的信号。 另一方面，脉冲宽度发生器还可以通过对与高频振荡器的环形振荡器示例性实施例的各个反相器级匹配的延迟线的各个反相器级进行抽头来适应高频振荡器周期的混合分数倍。

公开(公告)号：US20100141499A1

公开(公告)日：2010-06-10

申请号：US12329450

申请日：2008-12-05

申请人： Lennart K. Mathe

发明人： Lennart K. Mathe

IPC分类号： H03M1/12

CPC分类号： H03M1/462 ,  H03M1/466 ,  H03M1/804

摘要： A successive approximation analog-to-digital converter (ADC) includes a binary-weighted capacitor array, quantizer, and control block. One end of each capacitor is connected to the input of the quantizer, and a second end of each capacitor is controlled by the control block through a driver. A voltage is sampled, quantized, and stored as the most significant bit of the ADC's output. Depending on the result of the quantization, the control block toggles the driver of one of the capacitors corresponding to the most significant bit. The voltage at the common node is sampled again to obtain a second bit of the ADC's output. The operations are repeated as needed to obtain and store additional bits of the ADC's output. Similar configuration and process are described for a differential ADC. The operation is asynchronous, allowing extra time for metastable states only when such states occur.

摘要翻译： 逐次逼近模数转换器（ADC）包括二进制加权电容器阵列，量化器和控制块。 每个电容器的一端连接到量化器的输入，并且每个电容器的第二端由控制块通过驱动器控制。 电压被采样，量化并存储为ADC输出的最高有效位。 根据量化的结果，控制块切换对应于最高有效位的电容器之一的驱动器。 在公共节点处的电压被再次采样以获得ADC输出的第二位。 根据需要重复操作以获得并存储ADC输出的其他位。 差分ADC描述了类似的配置和过程。 该操作是异步的，只有当这种状态发生时才允许亚稳态的额外时间。

公开(公告)号：US07965134B2

公开(公告)日：2011-06-21

申请号：US12494068

申请日：2009-06-29

申请人： Vladimir Aparin ,  Namsoo Kim ,  Lennart K. Mathe

发明人： Vladimir Aparin ,  Namsoo Kim ,  Lennart K. Mathe

IPC分类号： H04B1/10

CPC分类号： H04B1/525 ,  H03F1/34 ,  H03F3/24 ,  H04B1/0475 ,  H04B1/109 ,  H04B1/123 ,  H04B2001/0433

摘要： Exemplary embodiments of the invention disclose signal filtering. In an exemplary embodiment, a filter device may comprise a subtractor operably coupled between an input and an output and configured to receive an input signal comprising a desired component and at least one undesired frequency component. The filter device may further include a feedback loop configured to receive at least one of the input signal and an output signal from the subtractor and convey a feedback signal comprising at least one undesired component to the subtractor. Each undesired component of the feedback signal corresponds to an associated undesired component of the input signal. Furthermore, the subtractor subtracts the feedback signal from the input signal and convey the output signal.

摘要翻译： 本发明的示例性实施例公开了信号滤波。 在示例性实施例中，滤波器装置可以包括可操作地耦合在输入端和输出端之间并被配置为接收包括期望分量和至少一个不需要的频率分量的输入信号的减法器。 滤波器装置还可以包括反馈回路，其被配置为从减法器接收输入信号和输出信号中的至少一个，并将包括至少一个不期望的分量的反馈信号传送到减法器。 反馈信号的每个不期望的分量对应于输入信号的相关不期望的分量。 此外，减法器从输入信号中减去反馈信号并传送输出信号。