公开(公告)号：US08078948B2

公开(公告)日：2011-12-13

申请号：US11576345

申请日：2005-09-28

申请人： Timothy Pontius ,  Jens Roever

发明人： Timothy Pontius ,  Jens Roever

IPC分类号： G06F11/00

CPC分类号： G06F13/4226

摘要： A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

摘要翻译： 数据通信布置允许使用两相协议在控制器模块和多个目标模块之间进行有效的数据传输。 控制器模块和目标模块可以分别驻留在不同的时钟域中。 与一个示例性实施例一致，数据通信装置包括多个目标模块和第一异或树，其被布置为提供第一数据完整性指示信号并且响应来自每个目标模块的各自的第二数据完整性指示信号 。 第二异或树被布置成提供第一数据总线并且响应来自每个目标模块的相应的第二数据总线。 此外，控制器模块用于响应于第一数据完整性指示信号来确定第一数据总线上的数据的可用性。

公开(公告)号：US20080270875A1

公开(公告)日：2008-10-30

申请号：US11576345

申请日：2005-09-28

申请人： Timothy A. Pontius ,  Jens Roever

发明人： Timothy A. Pontius ,  Jens Roever

IPC分类号： G06F11/00

CPC分类号： G06F13/4226

摘要： A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

摘要翻译： 数据通信布置允许使用两相协议在控制器模块和多个目标模块之间进行有效的数据传输。 控制器模块和目标模块可以分别驻留在不同的时钟域中。 与一个示例性实施例一致，数据通信装置包括多个目标模块和第一异或树，其被布置为提供第一数据完整性指示信号并且响应来自每个目标模块的各自的第二数据完整性指示信号 。 第二异或树被布置成提供第一数据总线并且响应来自每个目标模块的相应的第二数据总线。 此外，控制器模块用于响应于第一数据完整性指示信号来确定第一数据总线上的数据的可用性。

公开(公告)号：US20070011382A1

公开(公告)日：2007-01-11

申请号：US11165859

申请日：2005-06-24

申请人： Jens Roever

发明人： Jens Roever

IPC分类号： G06F13/14

CPC分类号： G06F13/1615 ,  G06F13/1663

摘要： A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline between a plurality of initiators and a shared resource. The multi-stage pipelined network includes first and second stages, where the first stage is disposed intermediate the second stage and the shared resource. First and second arbitration circuits are coupled respectively to the first and second stages of the multi-stage pipelined network, with each arbitration circuit configured to receive requests for access to the resource from at least one initiator and forward such requests to the shared resource. The second arbitration circuit is configured to forward requests to the shared resource via the first arbitration circuit, and the first arbitration circuit is configured to communicate at least one arbitration signal to the second arbitration circuit for use by the second arbitration circuit in arbitrating between requests received thereby. The incorporation of deferred arbitration logic enables arbitration logic to span levels of hierarchy, thus enabling the logical design of the memory-access structure to be effectively decoupled from the physical design.

摘要翻译： 电路布置和方法利用包含延迟仲裁逻辑的分级流水线存储器访问结构。 多级流水线网络定义多个启动器和共享资源之间的至少一个流水线。 多级流水线网络包括第一级和第二级，其中第一级布置在第二级和共享资源之间。 第一和第二仲裁电路分别耦合到多级流水线网络的第一级和第二级，每个仲裁电路被配置为从至少一个启动器接收对资源的访问请求，并将这些请求转发到共享资源。 第二仲裁电路被配置为经由第一仲裁电路将请求转发到共享资源，并且第一仲裁电路被配置为将至少一个仲裁信号传送到第二仲裁电路，供第二仲裁电路在所接收的请求之间进行仲裁 从而。 延迟仲裁逻辑的并入使得仲裁逻辑能够跨越层级，从而使存储器访问结构的逻辑设计能够有效地与物理设计分离。

公开(公告)号：US08543746B2

公开(公告)日：2013-09-24

申请号：US11917624

申请日：2006-06-23

申请人： Jens Roever

发明人： Jens Roever

IPC分类号： G06F13/00 ,  G06F3/00 ,  G06F5/00 ,  G06F13/36 ,  G06F1/04 ,  G06F1/12 ,  G06F15/16 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

CPC分类号： G06F13/4286 ,  H04N21/2381 ,  H04N21/4381 ,  H04N21/64322

摘要： A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).

摘要翻译： 电路布置和方法便于在生产者和消费者电路（12P，12C）之间直接传送数据，否则这些电路将被配置为通过基于地址的网络（18）进行通信。 从生成电路（12P）输出的数据流和由用户电路（12C）预期的传送数据流的请求中编址的地址信息中，为每个生产者和消费者电路（12P，12C）生成同步信号（46,56） 。 然后，用于生产者和消费者电路（12C）的同步信号（46,56）用于选择性地将由生产者电路（12P）输出的数据流修改为消费电路（12C）期望的格式。 通常，当消费者电路（12C）期望比生产者电路（12P）输出的数据更多的数据时，这种修改采用将数据插入到数据流中的形式，并且当消费者期望较少的时候丢弃由制造商电路（12P）传送的数据 数据比生成器电路（12P）输出的数据。

公开(公告)号：US07457894B2

公开(公告)日：2008-11-25

申请号：US09941478

申请日：2001-08-29

申请人： Jens Roever

发明人： Jens Roever

IPC分类号： G06F12/02

CPC分类号： G06F5/10 ,  G06F2205/108

摘要： A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided in a sequential manner within the block, but the sequence does not correspond to a higher-level sequence, due to a non-zero offset in the start of the sequence within the block, the memory access control is configured to optimize the use of available memory by signaling when the within-block sequence corresponds to the higher-level sequence. While the within-block sequence differs from the higher-level sequence, access to the buffer is limited to the higher-level partitioning of the buffer. When the within-block sequence corresponds to the higher-level sequence, access to the buffer is provided at the within-block partitioning of the buffer. In this manner, dependent upon the degree of offset of the within-block sequence relative to the higher-level sequence, access to the buffer is often provided well before the entire block is provided to the buffer, thereby optimizing the speed at which the memory can be accessed.

摘要翻译： 分级存储器访问控制区分已知顺序访问的数据块以及每个块的内容，其可以或可以不被顺序地访问。 如果在块内以顺序的方式提供块的内容，但是由于在该块内的序列开始时的非零偏移，该序列不对应于较高级别的序列，所以存储器访问控制 被配置为通过在块内序列对应于较高级序列的情况下通过信令来优化可用存储器的使用。 尽管块内序列与较高级别序列不同，但对缓冲区的访问仅限于缓冲区的较高级划分。 当内部块序列对应于较高级别序列时，在缓冲区的块内分区内提供对缓冲器的访问。 以这种方式，取决于片内序列相对于较高级别序列的偏移程度，通常在将整个块提供给缓冲器之前很好地提供对缓冲器的访问，从而优化存储器的速度 可以访问。

公开(公告)号：US20090300256A1

公开(公告)日：2009-12-03

申请号：US11917624

申请日：2006-06-23

申请人： Jens Roever

发明人： Jens Roever

IPC分类号： G06F13/28

CPC分类号： G06F13/4286 ,  H04N21/2381 ,  H04N21/4381 ,  H04N21/64322

摘要： A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).

摘要翻译： 电路布置和方法便于在生产者和消费者电路（12P，12C）之间直接传送数据，否则这些电路将被配置为通过基于地址的网络（18）进行通信。 从生成电路（12P）输出的数据流和由用户电路（12C）预期的传送数据流的请求中编址的地址信息中，为每个生产者和消费者电路（12P，12C）生成同步信号（46,56） 。 然后，用于生产者和消费者电路（12C）的同步信号（46,56）用于选择性地将由生产者电路（12P）输出的数据流修改为消费电路（12C）期望的格式。 通常，当消费者电路（12C）期望比生产者电路（12P）输出的数据更多的数据时，这种修改采用将数据插入到数据流中的形式，并且当消费者期望较少的时候丢弃由制造商电路（12P）传送的数据 数据比生成器电路（12P）输出的数据。