公开(公告)号：US20080270875A1

公开(公告)日：2008-10-30

申请号：US11576345

申请日：2005-09-28

申请人： Timothy A. Pontius ,  Jens Roever

发明人： Timothy A. Pontius ,  Jens Roever

IPC分类号： G06F11/00

CPC分类号： G06F13/4226

摘要： A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

摘要翻译： 数据通信布置允许使用两相协议在控制器模块和多个目标模块之间进行有效的数据传输。 控制器模块和目标模块可以分别驻留在不同的时钟域中。 与一个示例性实施例一致，数据通信装置包括多个目标模块和第一异或树，其被布置为提供第一数据完整性指示信号并且响应来自每个目标模块的各自的第二数据完整性指示信号 。 第二异或树被布置成提供第一数据总线并且响应来自每个目标模块的相应的第二数据总线。 此外，控制器模块用于响应于第一数据完整性指示信号来确定第一数据总线上的数据的可用性。

公开(公告)号：US06542855B1

公开(公告)日：2003-04-01

申请号：US09309137

申请日：1999-05-10

申请人： Timothy A. Pontius

发明人： Timothy A. Pontius

IPC分类号： G06F1500

CPC分类号： G06F11/3457 ,  G06F12/0802 ,  G06F2201/885

摘要： A method of selecting a cache design for a computer system begins with the making of a prototype module with a processor, a “seed” cache, and a trace detection module. The prototype module can be inserted within a system that includes main memory and peripherals. While an application program is run on the system, the communications between the processor and the seed cache are detected and compressed. The compressed detections are stored in a trace capture module and collectively define a trace of the program on the prototype module. The trace is then expanded and used to evaluate a candidate cache design. The expansion and evaluation can be iterated to evaluate many cache designs. The method can be used to pick the cache design with the best performance or as a foundation for performing a cost/performance comparison of the evaluated caches. In this method, a single prototype is used to generate an accurate trace that permits many alternative cache designs to be evaluated. This contrasts with methods that use cacheless models to develop less accurate traces and methods that allow only one cache design to be evaluated per prototype. In summary, the invention provides an accurate and efficient method of evaluating alternative cache designs.

摘要翻译： 选择用于计算机系统的高速缓存设计的方法开始于具有处理器，“种子”高速缓存和跟踪检测模块的原型模块的制造。 原型模块可以插入包含主存储器和外围设备的系统中。 当应用程序在系统上运行时，处理器和种子高速缓存之间的通信被检测和压缩。 压缩的检测存储在跟踪捕获模块中，并共同定义原型模块上程序的跟踪。 然后，跟踪被扩展并用于评估候选缓存设计。 可以迭代扩展和评估来评估许多缓存设计。 该方法可用于选择具有最佳性能的缓存设计或作为执行评估的缓存的成本/性能比较的基础。 在该方法中，使用单个原型来生成允许评估许多备用高速缓存设计的精确跟踪。 这与使用无高速缓存模型开发不太准确的跟踪和方法的方法形成对比，只允许每个原型对一个缓存设计进行评估。 总之，本发明提供了一种评估替代缓存设计的准确和有效的方法。

公开(公告)号：US06543030B1

公开(公告)日：2003-04-01

申请号：US09307165

申请日：1999-05-07

申请人： Liewei Bao ,  Timothy A. Pontius

发明人： Liewei Bao ,  Timothy A. Pontius

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F7/00

摘要： The timing characteristics of an integrated circuit design with an original combination-logic module can be potentially improved by moving an input signal with problematic timing in the original module so that it controls an output multiplexer in a revised module. The revised module includes two submodules. The first submodule provides the desired logic result where the late signal is low; the second submodule provides the desired logic result where the late signal is high. The multiplexer is controlled by the late signal so that its output is the desired logic result under steady-state conditions. If there are other input signals requiring timing advancement, the method can be reiterated. The method can be iterated until specifications are met or it is clear that the method cannot meet specifications by additional iterations.

摘要翻译： 具有原始组合逻辑模块的集成电路设计的定时特性可以通过在原始模块中移动具有有问题的定时的输入信号来进行改进，从而其在修改的模块中控制输出多路复用器。 修改后的模块包括两个子模块。 第一个子模块提供期望的逻辑结果，其中后期信号较低; 第二子模块提供期望的逻辑结果，其中后期信号为高。 多路复用器由延迟信号控制，使得其输出在稳态条件下是期望的逻辑结果。 如果存在需要定时提前的其他输入信号，则可以重申该方法。 该方法可以重复，直到满足规范或者清楚该方法不能通过附加迭代满足规范。

公开(公告)号：US06337893B1

公开(公告)日：2002-01-08

申请号：US09644348

申请日：2000-08-23

申请人： Timothy A. Pontius

发明人： Timothy A. Pontius

IPC分类号： H03K2364

CPC分类号： G06F5/14 ,  G06F2205/102 ,  G06F2205/106 ,  H03K23/005

摘要： A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and a register (14) that holds the pointer count). The binary incrementer increments by 1 except when the input is 0110 (decimal 6) or 1110 (decimal 14); in these cases, it increments by 3. The result is a 4-bit modulo-12 gray-code sequence with the twelve allowed gray-code values being distributed among the sixteen possible 4-bit gray code values with translational and reflective bilateral symmetry. The write pointer is similar. Because of the translational symmetry, detectors that work with counters with modulo numbers that are power of two work with the corresponding non-power-of-two counter to provide “full” and “empty” indications. When read and write counts differ at the two most-significant bit positions but are equal at the remaining bit positions, the detector provides a “full” indication for a 6-count FIFO. The gray-code counter design is scaleable to any non-power-of-two modulo number divisible by four.

摘要翻译： 用于基于RAM的FIFO的灰度计数器系统（AP1）包括读指针（10），写指针（20）和检测器（30）。读指针包括灰码解码器（11） 二进制加法器（12），灰度代码编码器（13）和保存指针计数的寄存器（14））。 二进制递增器递增1，除非输入为0110（十进制6）或1110（十进制14）; 在这些情况下，它增加3.结果是4位模12灰度序列，其中十二个允许的灰度值分布在具有平移和反射双边对称性的十六个可能的4位灰色码值中。 写指针是类似的。 由于平移对称性，使用具有模数的计数器的检测器是两个功能的计数器，与相应的非二功能计数器相结合来提供“完全”和“空”指示。 当读取和写入计数在两个最高有效位位置不同但在其余位位置相等时，检测器为6计数FIFO提供“满”指示。灰度计数器设计可扩展到任何非 - 四个幂除以模数。

公开(公告)号：US6029243A

公开(公告)日：2000-02-22

申请号：US934449

申请日：1997-09-19

申请人： Timothy A. Pontius ,  Kenneth A. Dockser

发明人： Timothy A. Pontius ,  Kenneth A. Dockser

IPC分类号： G06F7/57 ,  G06F9/30 ,  G06F9/38 ,  G06F9/302

CPC分类号： G06F7/483 ,  G06F9/3013 ,  G06F9/3861 ,  G06F9/3877 ,  G06F2207/382 ,  G06F7/49942

摘要： A floating-point processor nominally capable of single and double, but not extended, precision execution stores operands in extended-precision format. A format converter converts single and double precision source values to extended-precision format. Trap logic checks the apparent precision of the extended-precision operands and the requested result precision to determine whether the floating-point processor can execute the requested operation and yield the appropriate result. If the maximum of the requested precision and the maximum apparent precision of the operands is single or double, the requested operation is executed in hardware. Otherwise, a trap is issued to call an extended precision floating-point subroutine. This approach augments the class of operations that can be handled in hardware by a double-precision floating-point processor, and thus improves the floating-point computational throughput of an incorporating computer system.

摘要翻译： 一个标称能够单，双，但不扩展的精确执行的浮点处理器以扩展精度格式存储操作数。 格式转换器将单精度和双精度源值转换为扩展精度格式。 陷阱逻辑检查扩展精度操作数的表观精度和请求的结果精度，以确定浮点处理器是否可以执行请求的操作并产生适当的结果。 如果所请求的精度的最大值和操作数的最大表观精度是单精度或者倍数，则所请求的操作是以硬件方式执行的。 否则，将发出陷阱来调用扩展精度浮点子程序。 这种方法增加了可以通过双精度浮点处理器在硬件中处理的操作类，从而提高了并入的计算机系统的浮点计算吞吐量。

公开(公告)号：US06314154B1

公开(公告)日：2001-11-06

申请号：US09434218

申请日：1999-11-04

申请人： Timothy A. Pontius

发明人： Timothy A. Pontius

IPC分类号： G07C300

CPC分类号： H03K23/005

摘要： Non-power-of-two Gray-code counters, including modulos 10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register for storing an N-bit, e.g., 4-bit, Gray-code count. The count is converted to binary code by a Gray-to-binary-code counter. The resulting binary count is incremented by an N-bit incrementer that skips certain binary values by toggling least-significant bits in unison when indicated by certain most-significant binary bits. The result is converted to Gray-code by a binary-to-Gray-code translator. The translated result is stored in the register as the next count. An algorithm is disclosed for designing such a Gray-code counter for any even modulo. The modulo is expressed as a sum of positive and negative terms, each term being a power of two. The exponents of the terms determine the counter design.

摘要翻译： 公开了非功率二灰度代码计数器，包括模块10,12,14和22，以及它们使用的测序方法。 每个计数器包括用于存储N位，例如4位格雷码计数的寄存器。 计数通过灰色到二进制代码计数器转换为二进制代码。 所得到的二进制计数增加一个N位递增器，当由某些最重要的二进制位指示时，通过切换最低有效位同时跳过某些二进制值。 结果通过二进制到灰色代码转换器转换为格雷码。 翻译结果作为下一个计数存储在寄存器中。 公开了一种用于为任何均匀模数设计这样的格雷码计数器的算法。 模数表示为正和负项的和，每个项是2的幂。 这些术语的指数决定了计数器设计。

公开(公告)号：US06513105B1

公开(公告)日：2003-01-28

申请号：US09307164

申请日：1999-05-07

申请人： Timothy A. Pontius

发明人： Timothy A. Pontius

IPC分类号： G06F1200

CPC分类号： G06F5/10

摘要： A computer system includes a RAM-based FIFO for buffering communications between a host processor and a remote serial-communications device. The FIFO provides for quadlet, doublet, and singlet transfer widths depending on the memory-mapped IO address asserted by the processor. Quadlet transfers can be implemented until the amount of data remaining to be transferred is less than four bytes. For each quadlet transfer, the read pointer, in the case of a read operation, or the write pointer, in the case of a write operation, is incremented by four. If two or three bytes of data remain after the quadlet transfers, a doublet transfer can be implemented; in this case, the appropriate pointer is incremented by two. Finally, if a byte of data remains after the quadlet transfers and a possible doublet transfer, then a singlet transfer is effected. In this case, the appropriate pointer is incremented by one. For example, 31 bytes of data in an 8×4-byte FIFO can be transferred in seven quadlet transfers, one doublet transfer, and one byte-wide transfer. The use of the wide transfers greatly reduces the processor overhead in servicing the FIFO, making more processor power available to concurrently running tasks and improving system performance overall.

摘要翻译： 计算机系统包括用于缓冲主处理器和远程串行通信设备之间的通信的基于RAM的FIFO。 FIFO根据处理器断言的存储器映射的IO地址，提供quadlet，doublet和singlet传输宽度。 可以实现四边形传输，直到剩余的数据量少于四个字节。 对于每个quadlet传输，在读操作的情况下，读指针或写指针在写操作的情况下增加4。 如果在四字节传输之后仍然存在两个或三个字节的数据，则可以实现双重传输; 在这种情况下，适当的指针增加2。 最后，如果在字节传输之后的一个字节数据保持不变，并且可能的双向传输，则进行单重传输。 在这种情况下，适当的指针增加1。 例如，8x4字节FIFO中的31个字节的数据可以通过七个四字节传输，一个双工传输和一个字节宽的传输进行传输。 使用广泛的传输大大减少了处理FIFO的处理器开销，使更多的处理器能力可用于并发运行任务并提高整体系统性能。

公开(公告)号：US06507887B1

公开(公告)日：2003-01-14

申请号：US09551087

申请日：2000-04-18

申请人： Timothy A. Pontius ,  Gregory E. Ehmann

发明人： Timothy A. Pontius ,  Gregory E. Ehmann

IPC分类号： G06F1200

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G11C7/06 ,  G11C17/12 ,  G11C2207/2227 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

摘要： A method of designing a mask-programmable random-access read-only memory device begins with a step of assigning weightings to addresses according to their expected frequency of access. These weighting are used in a second step of determining for each sense amplifier, what is the low-power sense (inverted or uninverted) of the stored bits using that sense amplifier as an output. The third step involves storing the data in the low-power sense. The fourth step involves inverting the outputs for the data that is stored inverted. This can involve using sense inverting sense amplifiers for inverted data and sense preserving amplifiers for uninverted data. The method can result in memories in which some outputs are sense inverting while others are sense preserving. The result is a memory device with reduced power consumption relative to a comparable design not taking advantage of the relationship between data values and power consumption.

摘要翻译： 设计掩模可编程随机访问只读存储器设备的方法开始于根据其预期访问频率向地址分配加权的步骤。 这些加权用于确定每个读出放大器的第二步骤中，使用该读出放大器作为输出的存储位的低功率检测（反相或未反相）是多少。 第三步涉及将数据存储在低功耗意义上。 第四步涉及反转存储的数据的输出。 这可以涉及使用用于反相数据的感测反相读出放大器和用于未反转数据的感测保持放大器。 该方法可以导致其中一些输出是有意义的反相的存储器，而另一些是有意义的保留。 结果是相对于不利用数据值和功耗之间的关系的类似设计，具有降低的功耗的存储器件。

公开(公告)号：US5978437A

公开(公告)日：1999-11-02

申请号：US1116

申请日：1997-12-30

申请人： Timothy A. Pontius

发明人： Timothy A. Pontius

IPC分类号： H03K23/66 ,  H03K21/00

CPC分类号： H03K23/66

摘要： A counting system with a dynamic maximum count includes a counter, match logic, and a maximum count controller. The counter has a present count register, a clock (or event indicator) event input, and a reset input. The maximum count controller can be programmed with an adjustable maximum count stored in a maximum count register. The match logic includes a count-wide AND gate fed by NAND gates. Each NAND gate has an inverted input coupled to a respective bit position of the present count register and an uninverted input coupled to a respective bit position of the maximum count register. The function of the match logic is to indicate a match whenever the present count has a 1 at every bit position that the maximum count has a 1, irrespective of the present count values at bit positions at which the maximum count has 0s. Thus, imperfect matches are provided for. The values of the imperfect matches always exceed the values of perfect matches, so they are not usually encountered. However, in the case the maximum count is adjusted from above to below the present count, the invention achieves the desired change in rate of match indications more quickly than would be achieved if perfect matches were required. In addition, the match logic for the imperfect matches is simpler than the logic required for perfect matches. Thus, the invention provides both better functionality and a simpler implementation of a counting system.

摘要翻译： 具有动态最大计数的计数系统包括计数器，匹配逻辑和最大计数控制器。 计数器具有当前计数寄存器，时钟（或事件指示符）事件输入和复位输入。 最大计数控制器可以用存储在最大计数寄存器中的可调最大计数进行编程。 匹配逻辑包括由NAND门馈送的计数范围的AND门。 每个NAND门具有耦合到当前计数寄存器的相应位位置的反相输入和耦合到最大计数寄存器的相应位位置的未反相输入。 匹配逻辑的功能是在当前计数在每个位位置具有1的情况下指示匹配，即最大计数具有1，而与最大计数具有0的位位置处的当前计数值无关。 因此，提供了不完美的匹配。 不完全匹配的值总是超过完美匹配的值，因此通常不会遇到它们。 然而，在最大计数从上方调整到低于当前计数的情况下，如果需要完美匹配，本发明可以更快地实现匹配指示的期望变化。 此外，不完美匹配的匹配逻辑比完美匹配所需的逻辑简单。 因此，本发明提供更好的功能和更简单的计数系统的实现。