利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.018 秒)

    Dynamic pipeline reconfiguration including changing a number of stages
    2.
    发明授权
    Dynamic pipeline reconfiguration including changing a number of stages 有权
    动态管道重新配置，包括改变多个阶段

    公开(公告)号：US08806181B1

    公开(公告)日：2014-08-12

    申请号：US12434155

    申请日：2009-05-01

    申请人： R. Frank O'Bleness ,  Sujat Jamil ,  Timothy S. Beatty ,  Franco Ricci ,  Tom Hameenanttila ,  Hong-Yi Chen

    发明人： R. Frank O'Bleness ,  Sujat Jamil ,  Timothy S. Beatty ,  Franco Ricci ,  Tom Hameenanttila ,  Hong-Yi Chen

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3873 ,  G06F9/3869

    摘要： According to some embodiments, an apparatus having corresponding methods includes a storage module configured to store data and instructions; a first processor pipeline configured to process the data and instructions when the first processor pipeline is selected; a second processor pipeline configured to process the data and instructions when the second processor pipeline is selected; and a selection module configured to select either the first processor pipeline or the second processor pipeline.

    摘要翻译： 根据一些实施例，具有相应方法的装置包括被配置为存储数据和指令的存储模块; 配置为当选择所述第一处理器流水线时处理所述数据和指令的第一处理器流水线; 配置为当选择所述第二处理器管线时处理所述数据和指令的第二处理器流水线; 以及选择模块，被配置为选择第一处理器流水线或第二处理器流水线。

    Low power state retention
    3.
    发明授权
    Low power state retention 有权
    低功率状态保持

    公开(公告)号：US06775180B2

    公开(公告)日：2004-08-10

    申请号：US10329124

    申请日：2002-12-23

    申请人： Manish Biyani ,  Lawrence T. Clark ,  Shay P. Demmons ,  Franco Ricci

    发明人： Manish Biyani ,  Lawrence T. Clark ,  Shay P. Demmons ,  Franco Ricci

    IPC分类号： G11C1100

    CPC分类号： G11C5/145

    摘要： An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.

    摘要翻译： 一种具有状态保持存储器结构以存储状态值的集成电路。 高性能部分使用薄栅氧化物晶体管，并且状态保持存储器结构使用厚栅极氧化物晶体管来捕获并保持在低功率模式下工作时的状态值。

    Level shifter and voltage translator
    4.
    发明授权
    Level shifter and voltage translator 有权
    电平转换器和电压转换器

    公开(公告)号：US06774696B2

    公开(公告)日：2004-08-10

    申请号：US10318689

    申请日：2002-12-12

    申请人： Lawrence T. Clark ,  Shay P. Demmons ,  Franco Ricci ,  Tim Beatty

    发明人： Lawrence T. Clark ,  Shay P. Demmons ,  Franco Ricci ,  Tim Beatty

    IPC分类号： H03L500

    CPC分类号： H03K3/356156

    摘要： A level translator block receives a control signal and a data signal and provides an interface between circuitry operating in a first voltage domain and circuitry operating in a second voltage domain. Thick-oxide transistors are appropriately used in the level translator block to reduce gate leakage currents when translating signals.

    摘要翻译： 电平转换器块接收控制信号和数据信号，并提供在第一电压域中操作的电路和在第二电压域中工作的电路之间的接口。 在电平转换器块中适当地使用厚氧化物晶体管，以在转换信号时减少栅极漏电流。

    Low standby power using shadow storage
    5.
    发明授权
    Low standby power using shadow storage 有权
    低备用电源使用影子存储

    公开(公告)号：US06639827B2

    公开(公告)日：2003-10-28

    申请号：US10097202

    申请日：2002-03-12

    申请人： Lawrence T. Clark ,  Franco Ricci

    发明人： Lawrence T. Clark ,  Franco Ricci

    IPC分类号： G11C1100

    CPC分类号： G11C14/00

    摘要： An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses. The transistors having the thinner gate-oxide may be used to generate data values that may be stored by the transistors having the thicker gate-oxides. The thicker gate-oxides may reduce gate leakage currents during a system standby mode.

    摘要翻译： 具有以不同栅氧化物厚度处理的CMOS晶体管的集成电路。 具有较薄栅极氧化物的晶体管可用于产生可由具有较厚栅极氧化物的晶体管存储的数据值。 较厚的栅极氧化物可能在系统待机模式期间减小栅极泄漏电流。

    Memory address translations for programs code execution/relocation
    8.
    发明授权
    Memory address translations for programs code execution/relocation 失效
    程序代码执行/重定位的内存地址转换

    公开(公告)号：US5909702A

    公开(公告)日：1999-06-01

    申请号：US724610

    申请日：1996-09-30

    申请人： Marc Jalfon ,  David Regenold ,  Franco Ricci ,  Ramprasad Satagopan

    发明人： Marc Jalfon ,  David Regenold ,  Franco Ricci ,  Ramprasad Satagopan

    IPC分类号： G06F12/02 ,  G06F13/00

    CPC分类号： G06F12/0284

    摘要： A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space. This permits the program code to be loaded into any available page, and the processors can execute the code regardless of where it has been loaded, thereby permitting easy relocatability.

    摘要翻译： 多处理器数据处理系统包括专用数据总线和耦合到每个处理器的专用程序总线。 在专用数据总线之间耦合的是多个存储器组，每个存储体可以在处理器之间动态地切换以移动数据块，而无需将数据从一个存储体物理传送到另一个存储体。 同样地，多个存储体耦合在程序总线之间。 这些存储体通过共享总线从外部存储器加载程序指令页面。 任何一个页面都可以耦合到其各自的专用程序总线上的任一个处理器。 当页面耦合到共享总线时，它们显示为连续的地址空间。 当页面耦合到专用程序总线之一时，改变寻址模式，使得页面被映射到公共地址空间。 这允许将程序代码加载到任何可用的页面中，并且处理器可以执行代码，而不管它在哪里被加载，从而允许容易地重新定位。

    Selective shorting for clock grid during a controlling portion of a clock signal
    9.
    发明授权
    Selective shorting for clock grid during a controlling portion of a clock signal 失效
    在时钟信号的控制部分期间用于时钟网格的选择性短路

    公开(公告)号：US08607090B2

    公开(公告)日：2013-12-10

    申请号：US13036287

    申请日：2011-02-28

    申请人： Kim Schuttenberg ,  Franco Ricci

    发明人： Kim Schuttenberg ,  Franco Ricci

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10

    摘要： Systems, methods, and other embodiments associated with selective shorting are described. According to one embodiment, an apparatus includes a selective shorting device connected between clock branches. The selective shorting device is configured to selectively electrically connect the clock branches to one another and to selectively electrically disconnect the clock branches from one another. The apparatus also includes a selective shorting control mechanism that controls the selective shorting device to electrically connect the clock branches during a controlling portion of a clock signal. The selective shorting control mechanism is configured to electrically disconnect the clock branches in the absence of the controlling portion.

    摘要翻译： 描述了与选择性短路相关联的系统，方法和其他实施例。 根据一个实施例，一种装置包括连接在时钟分支之间的选择性短路装置。 选择性短路装置被配置为选择性地将时钟分支电连接到彼此并且选择性地将时钟分支彼此电断开。 该装置还包括选择性短路控制机构，其控制选通短路装置在时钟信号的控制部分期间电连接时钟分支。 选择性短路控制机构被配置为在没有控制部分的情况下电时断开时钟分支。

    State-retentive scan latch
    10.
    发明授权
    State-retentive scan latch 有权
    状态保持扫描锁存器

    公开(公告)号：US07796445B1

    公开(公告)日：2010-09-14

    申请号：US12029908

    申请日：2008-02-12

    申请人： Manish Biyani ,  Franco Ricci

    发明人： Manish Biyani ,  Franco Ricci

    IPC分类号： G11C7/00

    CPC分类号： G11C7/20 ,  G11C7/1045 ,  G11C19/28

    摘要： A device can include 1) a sustained or constantly powered low leakage latch to and from which a volatile state is uploaded and downloaded, respectively, based on an active-to-low signal, and 2) an intermittently powered or de-powerable memory element, coupled to the low leakage latch, from which and to which the volatile state is uploaded and downloaded, respectively, based on the active-to-low signal and a de-powerable voltage across the de-powerable memory element is powered and un-powered, respectively.

    摘要翻译： 一种设备可以包括：1）基于主动到低信号分别上传和下载易失性状态的持续或持续供电的低泄漏锁存器，以及2）间歇动力或不可动力的存储器元件 分别耦合到低泄漏锁存器，基于有源到低电平信号分别从其上下载易失性状态，并且通过不可操作的存储器元件上的去电力电压被供电和取消， 分别。