公开(公告)号：US07913132B2

公开(公告)日：2011-03-22

申请号：US12273985

申请日：2008-11-19

申请人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

发明人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

IPC分类号： G01R31/28

CPC分类号： G01R31/318536

摘要： A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.

摘要翻译： 公开了用于扫描顺序逻辑元件的数字系统和方法。 数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。 至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。 可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

公开(公告)号：US08312069B2

公开(公告)日：2012-11-13

申请号：US11872811

申请日：2007-10-16

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

IPC分类号： G06F7/00

CPC分类号： G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

摘要： A permute unit includes permute logic and a crossbar working in cycles defined by clocking signals and generates one valid output vector per cycle by treating two parallel input vectors per cycle. The permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals. In the first inner cycle, first halves of both input vectors are treated. In the second inner cycle, second halves of both input vectors are treated and a valid output vector is generated from the results of the treatments within the first and the second inner cycles.

摘要翻译： 置换单元包括置换逻辑和交叉开关，其周期由定时信号定义，并且通过每个周期处理两个并行输入向量来产生每个周期的一个有效输出向量。 置换单元通过每个外部周期执行两个内部循环由时钟信号定义来进行双重泵浦。 在第一个内循环中，处理两个输入向量的前半部分。 在第二内循环中，处理两个输入向量的第二半，并且从第一和第二内循环中的处理结果生成有效的输出向量。

公开(公告)号：US20090135961A1

公开(公告)日：2009-05-28

申请号：US12273985

申请日：2008-11-19

申请人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

发明人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

IPC分类号： H04L27/06

CPC分类号： G01R31/318536

摘要： System and Method for Scanning Sequential Logic Elements A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.

摘要翻译： 用于扫描顺序逻辑元件的系统和方法公开了用于扫描顺序逻辑元件的数字系统和方法。 数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。 至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。 可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

公开(公告)号：US20080130871A1

公开(公告)日：2008-06-05

申请号：US11872811

申请日：2007-10-16

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

IPC分类号： H04L9/28

CPC分类号： G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

摘要： A permute unit is described comprising a permute logic and a crossbar working in cycles defined by clocking signals and generating one valid output vector per cycle by treating two parallel input vectors per cycle according to an adequate scheme, wherein the permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals, wherein in every first inner cycle first halves of both input vectors are treated and in every second inner cycle second halves of both input vectors are treated and wherein every second inner cycle a valid output vector is generated from the results of the treatments within the first and the second inner cycles. Furthermore a method is described to operate such a permute unit.

摘要翻译： 描述了一种置换单元，其包括按照由时钟信号定义的周期工作的交替项，并且根据适当的方案通过每个周期处理两个并行输入向量来产生每个周期的一个有效输出向量，其中，通过执行 每个外部循环由时钟信号定义的每个外部周期的两个内部循环，其中在每个第一内部循环中处理两个输入向量的前半部分，并且在每个第二内部循环中处理两个输入向量的第二半部，并且其中每个第二内部循环有效输出向量 是从第一和第二内循环中的处理结果产生的。 此外，描述了操作这种置换单元的方法。

公开(公告)号：US07795914B2

公开(公告)日：2010-09-14

申请号：US12262255

申请日：2008-10-31

申请人： Tobias Gemmeke ,  Friedrich Schroeder ,  Stefan Bonsels ,  Dieter Wendel

发明人： Tobias Gemmeke ,  Friedrich Schroeder ,  Stefan Bonsels ,  Dieter Wendel

IPC分类号： H03K19/00 ,  H03K19/02

CPC分类号： H03K19/09429 ,  H03K19/0016

摘要： A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage. The three stage circuit is switched to a low leakage state by a control signal feed via the control input and setting the two transistors in their off state resulting in a second stage with a floating common output filtered by the third stage via the control signal actively driven the data output to a specific logic value.

摘要翻译： 根据本发明的三级电路包括数据输入，数据输出，控制输入，两个电压输入。 第一级电连接到数据输入和控制输入，并由具有两个输出的组合电路定义。 第二级由两个电压源输入之间串联连接的至少两个晶体管形成，它们的输入电连接到第一级的相应输出，并具有共同的输出，使得与第一级连接时，它们以三 状态门 该三级电路的第三级电连接到第二级的控制输入和公共输出端。 三级电路经由控制输入端通过控制信号馈电切换到低泄漏状态，并将两个晶体管设置为关闭状态，从而产生第二级，其中第一级通过主动驱动的控制信号由第三级滤波的浮动公共输出 数据输出到一个特定的逻辑值。

公开(公告)号：US20090115504A1

公开(公告)日：2009-05-07

申请号：US12262255

申请日：2008-10-31

申请人： Tobias Gemmeke ,  Friedrich Schroeder ,  Stefan Bonsels ,  Dieter Wendel

发明人： Tobias Gemmeke ,  Friedrich Schroeder ,  Stefan Bonsels ,  Dieter Wendel

IPC分类号： H01L25/00

CPC分类号： H03K19/09429 ,  H03K19/0016

摘要： A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage. The three stage circuit is switched to a low leakage state by a control signal feed via the control input and setting the two transistors in their off state resulting in a second stage with a floating common output filtered by the third stage via the control signal actively driven the data output to a specific logic value.

摘要翻译： 根据本发明的三级电路包括数据输入，数据输出，控制输入，两个电压输入。 第一级电连接到数据输入和控制输入，并由具有两个输出的组合电路定义。 第二级由两个电压源输入之间串联连接的至少两个晶体管形成，它们的输入电连接到第一级的相应输出，并具有共同的输出，使得与第一级连接时，它们以三 状态门 该三级电路的第三级电连接到第二级的控制输入和公共输出端。 三级电路经由控制输入端通过控制信号馈电切换到低泄漏状态，并将两个晶体管设置为关闭状态，从而产生第二级，其中第一级通过主动驱动的控制信号由第三级滤波的浮动公共输出 数据输出到一个特定的逻辑值。

公开(公告)号：US07844799B2

公开(公告)日：2010-11-30

申请号：US09683383

申请日：2001-12-20

申请人： Jens Leenstra ,  Antje Mueller ,  Juergen Pille ,  Dieter Wendel

发明人： Jens Leenstra ,  Antje Mueller ,  Juergen Pille ,  Dieter Wendel

IPC分类号： G06F9/30 ,  G06F9/34

CPC分类号： G06F9/3873 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： A method and system for operating a high frequency out-of-order processor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called “no dependency” for an instruction. A “no dependency” signal tells that all required source data is available for the instruction at least one cycle before the source data valid bit(s) are inserted into the issue queue. Therefore, one or more stages of the pipeline are bypassed.

摘要翻译： 一种用于操作具有增加的管道长度的高频无序处理器的方法和系统。 公开了一种新方案，通过对指令的所谓“不依赖”的检测和利用来减少流水线。 “无依赖”信号指示在将源数据有效位插入到发出队列之前至少一个周期，所有必需的源数据可用于指令。 因此，管道的一个或多个阶段被绕过。

公开(公告)号：US06829699B2

公开(公告)日：2004-12-07

申请号：US09683391

申请日：2001-12-20

申请人： Jens Leenstra ,  Dieter Wendel

发明人： Jens Leenstra ,  Dieter Wendel

IPC分类号： G06F938

CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： An improved method and system for operating an out of order processor at a high frequency enabled by an increased pipeline length. It is proposed to shorten the pipeline by a considerable number of stages by accepting that a write after read conflict may occur, when directly after renaming, during the “read ROB” pipeline stage, all the information (tag, validity and data) is read from an Reorder Buffer ROB entry, and is next written, in a following pipeline stage “write RS”, into a reservation station (RS) entry. In order to assure the correctness of processing in particular in cases of dependencies, e.g., write after read conflicts a separate inventional add in logic covers these cases. The logic detects the write after read conflict case of an Instructional Execution Unit (IEU) writing into the particular entry that is selected by the renaming logic during “read ROB”. Then, a separate issue process selects the entries for which a conflict is reported and writes the data into the respective entry of the RS. This increases performance because those conflict cases are rather seldom compared to the broad majority of instructions to be found in a statistically determined average instruction flow.

摘要翻译： 一种改进的方法和系统，用于通过增加的流水线长度在高频下操作无序处理器。 建议通过接受在读取冲突之后写入，直接在重命名之后，在“读取ROB”流水线阶段期间，可以读取所有信息（标签，有效性和数据），缩短流水线 来自重排序缓冲器ROB条目，并且在下一个流水线级“写入RS”中被写入保留站（RS）条目。 为了确保处理的正确性，特别是在依赖性的情况下，例如在读取冲突之后写入，单独的发明逻辑将覆盖这些情况。 该逻辑检测指令执行单元（IEU）写入读写冲突之后的写入到在“读取ROB”期间由重命名逻辑选择的特定条目。 然后，单独的问题过程选择报告冲突的条目，并将数据写入RS的相应条目。 这增加了性能，因为这些冲突案例与在统计确定的平均指令流程中找到的大多数指令相比很少。

公开(公告)号：US06918119B2

公开(公告)日：2005-07-12

申请号：US09838068

申请日：2001-04-19

申请人： Wilhelm E. Haller ,  Jens Leenstra ,  Rolf Sautter ,  Dieter Wendel ,  Friedrich-Christian Wernicke

发明人： Wilhelm E. Haller ,  Jens Leenstra ,  Rolf Sautter ,  Dieter Wendel ,  Friedrich-Christian Wernicke

IPC分类号： G06F5/10 ,  G06F9/38 ,  G06F3/00

CPC分类号： G06F5/10 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： The present invention relates to a method and system for determining the status of each entry in an instruction window buffer in multi-processor, parallel processing environments. A combinatorial circuit, which automatically generates active instruction window status information, is added to the buffer itself. This status information is used by a plurality of processes like renaming registers and issuing and committing instructions as an output associated with a respective buffer entry.

摘要翻译： 本发明涉及一种用于在多处理器并行处理环境中确定指令窗口缓冲器中的每个条目的状态的方法和系统。 自动生成活动指令窗口状态信息的组合电路被添加到缓冲器本身。 该状态信息被诸如重命名寄存器和发出和提交指令之类的多个进程用作与相应缓冲器条目相关联的输出。

公开(公告)号：US06785781B2

公开(公告)日：2004-08-31

申请号：US09825072

申请日：2001-04-03

申请人： Jens Leenstra ,  Juergen Pille ,  Rolf Sautter ,  Dieter Wendel

发明人： Jens Leenstra ,  Juergen Pille ,  Rolf Sautter ,  Dieter Wendel

IPC分类号： G06F1200

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G11C8/16

摘要： A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.

摘要翻译： 根据本发明，通过将输入端口的数量和输出端口的数量减少到同时预期的阵列访问的数量n，可以节省相当多的面积。 当利用关于阵列利用的一些知识时，可以实现端口的显着减少，从而实现非常相关的区域保存：阵列访问将由最多k个特定组的并发访问执行。 一组由多个阵列访问定义，每次访问至多一次访问同一个端口。 然后，为了读取，读取结果根据简单的重新布线方案对齐到相应的读取请求者，而对于写入，根据相同或相似的方案在阵列访问之前进行对齐。