公开(公告)号：US07913132B2

公开(公告)日：2011-03-22

申请号：US12273985

申请日：2008-11-19

申请人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

发明人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

IPC分类号： G01R31/28

CPC分类号： G01R31/318536

摘要： A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.

摘要翻译： 公开了用于扫描顺序逻辑元件的数字系统和方法。 数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。 至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。 可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

公开(公告)号：US08312069B2

公开(公告)日：2012-11-13

申请号：US11872811

申请日：2007-10-16

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

IPC分类号： G06F7/00

CPC分类号： G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

摘要： A permute unit includes permute logic and a crossbar working in cycles defined by clocking signals and generates one valid output vector per cycle by treating two parallel input vectors per cycle. The permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals. In the first inner cycle, first halves of both input vectors are treated. In the second inner cycle, second halves of both input vectors are treated and a valid output vector is generated from the results of the treatments within the first and the second inner cycles.

摘要翻译： 置换单元包括置换逻辑和交叉开关，其周期由定时信号定义，并且通过每个周期处理两个并行输入向量来产生每个周期的一个有效输出向量。 置换单元通过每个外部周期执行两个内部循环由时钟信号定义来进行双重泵浦。 在第一个内循环中，处理两个输入向量的前半部分。 在第二内循环中，处理两个输入向量的第二半，并且从第一和第二内循环中的处理结果生成有效的输出向量。

公开(公告)号：US20090135961A1

公开(公告)日：2009-05-28

申请号：US12273985

申请日：2008-11-19

申请人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

发明人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

IPC分类号： H04L27/06

CPC分类号： G01R31/318536

摘要： System and Method for Scanning Sequential Logic Elements A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.

摘要翻译： 用于扫描顺序逻辑元件的系统和方法公开了用于扫描顺序逻辑元件的数字系统和方法。 数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。 至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。 可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

公开(公告)号：US20080130871A1

公开(公告)日：2008-06-05

申请号：US11872811

申请日：2007-10-16

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

IPC分类号： H04L9/28

CPC分类号： G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

摘要： A permute unit is described comprising a permute logic and a crossbar working in cycles defined by clocking signals and generating one valid output vector per cycle by treating two parallel input vectors per cycle according to an adequate scheme, wherein the permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals, wherein in every first inner cycle first halves of both input vectors are treated and in every second inner cycle second halves of both input vectors are treated and wherein every second inner cycle a valid output vector is generated from the results of the treatments within the first and the second inner cycles. Furthermore a method is described to operate such a permute unit.

摘要翻译： 描述了一种置换单元，其包括按照由时钟信号定义的周期工作的交替项，并且根据适当的方案通过每个周期处理两个并行输入向量来产生每个周期的一个有效输出向量，其中，通过执行 每个外部循环由时钟信号定义的每个外部周期的两个内部循环，其中在每个第一内部循环中处理两个输入向量的前半部分，并且在每个第二内部循环中处理两个输入向量的第二半部，并且其中每个第二内部循环有效输出向量 是从第一和第二内循环中的处理结果产生的。 此外，描述了操作这种置换单元的方法。

公开(公告)号：US07735038B2

公开(公告)日：2010-06-08

申请号：US11850745

申请日：2007-09-06

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： H03K19/0016

摘要： A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.

摘要翻译： 一种用于降低时钟门控同步电路内的功耗的设计结构，所述同步电路包括至少两个连续级，其中每个级如果被激活，则逐周期地将数据信号周期传播到后级，所述两个连续级包括至少一个控制寄存器 ，数据寄存器和本地时钟缓冲器（LCB），其中每个级如果被激活，则将周期内存储的数据信号周期传播到后级的数据寄存器。

公开(公告)号：US07890901B2

公开(公告)日：2011-02-15

申请号：US11684899

申请日：2007-03-12

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Nicolas Maeding ,  Hari Mony

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Nicolas Maeding ,  Hari Mony

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/504

摘要： The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.

摘要翻译： 比较了数字电路的等效设计的自动验证，其中以不同的硬件描述语言（HDL）实现的逻辑设计和不同的设计方法进行了比较。 通过添加特殊包装器（Wrapper A，Wrapper B）来修改设计（代码A，代码B），并用于均衡所选输入信号对的时序和逻辑设计的选定输出信号。 封装器驱动与实际比较无关的设计的某些信号，包括时钟信号，时钟控制信号，扫描路径信号，扫描路径控制信号和复位信号等信号。 在优选实施例中，分析逻辑设计的HDL描述。 基于这种分析，包装器被实现为对HDL描述的改变。 在另一个实施例中，分析和修改RTL和/或门级网表。

公开(公告)号：US20070226664A1

公开(公告)日：2007-09-27

申请号：US11684899

申请日：2007-03-12

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Nicolas Maeding ,  Hari Mony

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Nicolas Maeding ,  Hari Mony

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.

摘要翻译： 比较了数字电路的等效设计的自动验证，其中以不同的硬件描述语言（HDL）实现的逻辑设计和不同的设计方法进行了比较。 通过添加特殊包装器（Wrapper A，Wrapper B）来修改设计（代码A，代码B），并用于均衡所选输入信号对的时序和逻辑设计的选定输出信号。 封装器驱动与实际比较无关的设计的某些信号，包括时钟信号，时钟控制信号，扫描路径信号，扫描路径控制信号和复位信号等信号。 在优选实施例中，分析逻辑设计的HDL描述。 基于这种分析，包装器被实现为对HDL描述的改变。 在另一个实施例中，分析和修改RTL和/或门级网表。

公开(公告)号：US07962538B2

公开(公告)日：2011-06-14

申请号：US11560165

申请日：2006-11-15

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Nicolas Maeding ,  Kerstin Schelm

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Nicolas Maeding ,  Kerstin Schelm

IPC分类号： G06F7/00 ,  G06F15/00 ,  G06F7/50 ,  G06F7/38

CPC分类号： G06F7/49921

摘要： An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M

摘要翻译： 一种电子计算电路，用于实现一种将比特长度N减小到比特长度M的两个操作数的比特宽度的方法，因此，M

公开(公告)号：US20070165343A1

公开(公告)日：2007-07-19

申请号：US11553037

申请日：2006-10-26

申请人： Harry Barowski ,  Sebastian Ehrenreich ,  Tobias Gemmeke ,  Jens Leenstra

发明人： Harry Barowski ,  Sebastian Ehrenreich ,  Tobias Gemmeke ,  Jens Leenstra

IPC分类号： H02H9/08

CPC分类号： H03K19/0016 ,  G06F1/32

摘要： A Circuit arrangement to reduce leakage power and to increase the performance of a circuit comprising three electric potentials is described, wherein a diode is arranged between the third and the second or first electric potential to obtain a potential drop of the third electric potential and parallel to said diode a switch is arranged between the third and the second or between the third and the first electric potential to change the potential drop of the third electric potential opposite to the first or the second electric potential about the voltage drop of said diode wherein said switch comprises a transistor having a broad transistor channel. Furthermore a method to reduce leakage power and to increase the performance of a circuit by using said circuit arrangement is described.

摘要翻译： 描述了一种降低泄漏功率并增加包括三个电势的电路的性能的电路装置，其中二极管被布置在第三和第二或第一电位之间以获得第三电位的电位降并平行于 所述二极管的开关被布置在第三和第二之间或者在第三和第一电位之间，以改变与围绕所述二极管的电压降的第一或第二电位相反的第三电位的电势降，其中所述开关 包括具有宽晶体管沟道的晶体管。 此外，描述了通过使用所述电路装置来减少漏电功率和提高电路性能的方法。

公开(公告)号：US07639046B2

公开(公告)日：2009-12-29

申请号：US11850736

申请日：2007-09-06

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

IPC分类号： H03K19/00 ,  H03K17/16 ,  H03K19/003 ,  G06F1/00 ,  G05F1/10 ,  G05F3/02

CPC分类号： H03K19/0016

摘要： A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.

摘要翻译： 一种降低时钟门控同步电路内的功耗的方法，所述同步电路包括至少两个连续的级，其中每个阶段如果被激活，则将周期性的数据信号周期传播到后一级，包括以下步骤：导出本地时钟激活 来自外部时钟激活信号的信号，其中所述本地时钟激活信号每周期改变其值，外部时钟激活信号指示传播，数据信号和本地时钟激活信号从一个特定阶段到后一个周期循环传播 每当通过从时钟激活信号导出或通过传播通过同步电路在特定阶段的本地时钟激活信号在两个连续周期之间改变其值时，为了在同一时钟域内传播数据信号和本地时钟激活信号 通过时钟门控同步电路。