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    Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a Circuit
    1.
    发明申请
    Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a Circuit 审中-公开
    电路布置和降低漏电功率和提高电路性能的方法

    公开(公告)号：US20070165343A1

    公开(公告)日：2007-07-19

    申请号：US11553037

    申请日：2006-10-26

    申请人： Harry Barowski ,  Sebastian Ehrenreich ,  Tobias Gemmeke ,  Jens Leenstra

    发明人： Harry Barowski ,  Sebastian Ehrenreich ,  Tobias Gemmeke ,  Jens Leenstra

    IPC分类号： H02H9/08

    CPC分类号： H03K19/0016 ,  G06F1/32

    摘要： A Circuit arrangement to reduce leakage power and to increase the performance of a circuit comprising three electric potentials is described, wherein a diode is arranged between the third and the second or first electric potential to obtain a potential drop of the third electric potential and parallel to said diode a switch is arranged between the third and the second or between the third and the first electric potential to change the potential drop of the third electric potential opposite to the first or the second electric potential about the voltage drop of said diode wherein said switch comprises a transistor having a broad transistor channel. Furthermore a method to reduce leakage power and to increase the performance of a circuit by using said circuit arrangement is described.

    摘要翻译： 描述了一种降低泄漏功率并增加包括三个电势的电路的性能的电路装置，其中二极管被布置在第三和第二或第一电位之间以获得第三电位的电位降并平行于 所述二极管的开关被布置在第三和第二之间或者在第三和第一电位之间，以改变与围绕所述二极管的电压降的第一或第二电位相反的第三电位的电势降，其中所述开关 包括具有宽晶体管沟道的晶体管。 此外，描述了通过使用所述电路装置来减少漏电功率和提高电路性能的方法。

    Method and system for data dependent performance increment and power reduction
    2.
    发明授权
    Method and system for data dependent performance increment and power reduction 失效
    数据相关性能增量和功耗降低的方法和系统

    公开(公告)号：US07502918B1

    公开(公告)日：2009-03-10

    申请号：US12058256

    申请日：2008-03-28

    申请人： Harry Barowski ,  Tobias Gemmeke ,  Tim Niggemeier ,  Thomas Pflueger

    发明人： Harry Barowski ,  Tobias Gemmeke ,  Tim Niggemeier ,  Thomas Pflueger

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/384

    摘要： A method of dispatching instructions includes dispatching original instructions into an instruction buffer, including at least one operand, renaming the operand, selecting the original instructions from the instruction buffer, sending selected instructions with explicit bits, to an internal operation code exchange table, which includes replacement rules for replacing the selected instructions with a simplified instruction based on the original instructions and the explicit bits, replacing the selected instructions with the simplified instruction in accordance with the explicit bits, and issuing the simplified instructions to an execution unit by sending the simplified instruction and all explicit bits for the operands to a content addressable memory address logic of the internal operation code exchange table, wherein if a bitvector, consisting of the original instruction and the explicit bits, matches a pattern stored in the internal operation code exchange table, the original instruction is replaced by the simplified instruction.

    摘要翻译： 一种调度指令的方法包括将指令分配到指令缓冲器中，该指令缓冲器包括至少一个操作数，重新命名操作数，从指令缓冲器中选择原始指令，向显示位发送所选择的指令给内部操作代码交换表，其包括 基于原始指令和显式位用简化指令替换所选指令的替换规则，根据显式位用简化指令代替所选指令，并通过发送简化指令将简化指令发送到执行单元 以及用于操作数的所有显式位到内部操作代码交换表的内容可寻址存储器地址逻辑，其中如果由原始指令和显式位组成的位向量与存储在内部操作代码交换表中的模式匹配， 原来的指示 离子被简化的指令代替。

    Formally deriving a minimal clock-gating scheme
    3.
    发明申请
    Formally deriving a minimal clock-gating scheme 有权
    正式推出最小的时钟门控方案

    公开(公告)号：US20080288901A1

    公开(公告)日：2008-11-20

    申请号：US12107940

    申请日：2008-04-23

    申请人： Harry Barowski ,  J. Adam Butts ,  Tobias Gemmeke ,  Nicolas Maeding ,  Viresh Paruthi

    发明人： Harry Barowski ,  J. Adam Butts ,  Tobias Gemmeke ,  Nicolas Maeding ,  Viresh Paruthi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/504 ,  G06F17/505 ,  G06F2217/78

    摘要： The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.

    摘要翻译： 本发明提供了一种全自动的方法，用于获得由于时钟选通而具有最小功耗的电路。 要优化的电路设计被修改为减少功率修改的设计并且与时钟门控方案相关联。 验证工具将修改后的设计与原始设计进行比较，以确定是否可以使用修改后的设计。 可以重复进行进一步的修改，直到实现最佳设计。

    Formally deriving a minimal clock-gating scheme
    4.
    发明授权
    Formally deriving a minimal clock-gating scheme 有权
    正式推出最小的时钟门控方案

    公开(公告)号：US07849428B2

    公开(公告)日：2010-12-07

    申请号：US12107940

    申请日：2008-04-23

    申请人： Harry Barowski ,  J. Adam Butts ,  Tobias Gemmeke ,  Nicolas Maeding ,  Viresh Paruthi

    发明人： Harry Barowski ,  J. Adam Butts ,  Tobias Gemmeke ,  Nicolas Maeding ,  Viresh Paruthi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/504 ,  G06F17/505 ,  G06F2217/78

    摘要： The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.

    摘要翻译： 本发明提供了一种全自动的方法，用于获得由于时钟选通而具有最小功耗的电路。 要优化的电路设计被修改为减少功率修改的设计并且与时钟门控方案相关联。 验证工具将修改后的设计与原始设计进行比较，以确定是否可以使用修改后的设计。 可以重复进行进一步的修改，直到实现最佳设计。

    MULTI-CYCLE REGISTER FILE BYPASS
    5.
    发明申请
    MULTI-CYCLE REGISTER FILE BYPASS 审中-公开
    多周期寄存器文件旁路

    公开(公告)号：US20090249035A1

    公开(公告)日：2009-10-01

    申请号：US12058043

    申请日：2008-03-28

    申请人： Harry Barowski ,  Tobias Gemmeke ,  Nicolas Maeding ,  Tim Niggemeier

    发明人： Harry Barowski ,  Tobias Gemmeke ,  Nicolas Maeding ,  Tim Niggemeier

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3826 ,  G06F9/30141 ,  G06F9/3832

    摘要： A method of reducing latency in instruction processing in a system, includes calculating a result of a first execution unit, storing the result of the first execution unit in a register file, forwarding the result of the first execution unit, through the bypass unit, to a second execution unit, the second execution unit conducting an instruction dependent on the result, forwarding the result of the first execution unit, from the bypass unit, to a third execution unit, without accessing the register file, the third execution unit conducting an instruction dependent on the result, wherein the execution units can extract the result of the first execution unit through the bypass unit until the new result is calculated, wherein after the new result is calculated, the execution units can access the result of the first execution unit through the register file.

    摘要翻译： 一种减少系统中指令处理的延迟的方法，包括：计算第一执行单元的结果，将第一执行单元的结果存储在寄存器文件中，并将第一执行单元的结果通过旁路单元转发到 第二执行单元，所述第二执行单元执行取决于所述结果的指令，将所述第一执行单元的结果从所述旁路单元转发到第三执行单元，而不访问所述寄存器文件，所述第三执行单元执行指令 取决于结果，其中执行单元可以通过旁路单元提取第一执行单元的结果，直到计算新结果，其中在计算新结果之后，执行单元可以通过以下方式访问第一执行单元的结果： 注册文件。

    Method to Reduce Leakage Within a Sequential Network and Latch Circuit
    6.
    发明申请
    Method to Reduce Leakage Within a Sequential Network and Latch Circuit 审中-公开
    降低连续网络和锁存电路泄漏的方法

    公开(公告)号：US20070168792A1

    公开(公告)日：2007-07-19

    申请号：US11566462

    申请日：2006-12-04

    申请人： Harry Barowski ,  Tobias Gemmeke ,  Christian Jacobi ,  Matthias Pflanz

    发明人： Harry Barowski ,  Tobias Gemmeke ,  Christian Jacobi ,  Matthias Pflanz

    IPC分类号： G01R31/28

    CPC分类号： H03K19/0016 ,  G01R31/318541 ,  H03K3/0372 ,  H03K3/0375

    摘要： A method to reduce leakage within a sequential network comprising at least one latch and a combinatorial logic proximate to said latch, by applying an input vector on said sequential network during idle mode is described, the method comprising the steps of: overriding a static feedback of a latch comprising a static feedback loop with an input vector, and setting said sequential network into idle mode. Furthermore a latch circuit comprising a static feedback loop, to be used to perform said method is described, wherein said latch circuit comprises means to override a static feedback within said static feedback loop with an input vector before falling in idle mode.

    摘要翻译： 描述了一种通过在空闲模式期间通过在所述顺序网络上施加输入向量来减少包括至少一个锁存器和靠近所述锁存器的组合逻辑的顺序网络内的泄漏的方法，所述方法包括以下步骤：重写静态反馈 锁存器，其包括具有输入向量的静态反馈回路，以及将所述顺序网络设置为空闲模式。 此外，描述了包括用于执行所述方法的静态反馈回路的锁存电路，其中所述锁存电路包括在落入空闲模式之前用输入向量来覆盖所述静态反馈回路内的静态反馈的装置。

    Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independent
    8.
    发明授权
    Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independent 有权
    当指令的发布率低于阈值并且至少两个是独立的时，关闭执行单元以发出指令累加

    公开(公告)号：US08806253B2

    公开(公告)日：2014-08-12

    申请号：US13569809

    申请日：2012-08-08

    申请人： Tim Niggemeier ,  Harry Barowski ,  Maarten Boersma ,  Gunnar Spiess

    发明人： Tim Niggemeier ,  Harry Barowski ,  Maarten Boersma ,  Gunnar Spiess

    IPC分类号： G06F1/32 ,  G06F9/38

    CPC分类号： G06F1/3287 ,  G06F1/3206 ,  G06F1/3234 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3871

    摘要： A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decoder; an execution unit receiving and sending signals from and to the instruction scheduling unit; and a state machine. The method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a signal from the state machine.

    摘要翻译： 一种具有指令调度单元的微处理器的电源门控方法，用于从指令解码器接收发出的指令; 执行单元从指令调度单元接收和发送信号; 和状态机。 该方法包括：获得每个周期的指令数量，发出给指令调度单元; 确定如果发出给指令调度单元的每个周期的指令数量小于阈值水平，然后确定发出到指令调度单元的至少两个指令是否相互独立，只有当每个指令 周期小于阈值水平; 确定发出到指令调度单元的指令中的至少两个是否彼此独立; 和电源门控微处理器通过来自状态机的信号关闭空闲宏的电源。

    METHOD AND APPARATUS FOR IMPROVED POWER MANAGEMENT OF MICROPROCESSORS BY INSTRUCTION GROUPING
    10.
    发明申请
    METHOD AND APPARATUS FOR IMPROVED POWER MANAGEMENT OF MICROPROCESSORS BY INSTRUCTION GROUPING 失效
    通过指令分组改进微处理器功率管理的方法和装置

    公开(公告)号：US20100228955A1

    公开(公告)日：2010-09-09

    申请号：US12397830

    申请日：2009-03-04

    申请人： Tim Niggemeier ,  Harry Barowski ,  Maarten Boersma ,  Gunnar Spiess

    发明人： Tim Niggemeier ,  Harry Barowski ,  Maarten Boersma ,  Gunnar Spiess

    IPC分类号： G06F9/312

    CPC分类号： G06F1/3287 ,  G06F1/3206 ,  G06F1/3234 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3871

    摘要： A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decode unit; an execution unit coupled to receive and send signals from and to the instruction scheduling unit; and a state machine located within the execution unit, the method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, subsequent to obtaining the number of instructions per cycle, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a signal from the state machine when the instructions are independent of each other without incurring significant loss of performance until an issue queue in the instruction scheduling unit is filled with instruction data.

    摘要翻译： 一种具有指令调度单元的微处理器的电源门控方法，用于从指令解码单元接收发出的指令; 执行单元，被耦合以从所述指令调度单元接收和发送信号; 以及位于所述执行单元内的状态机，所述方法包括：获取每个循环的指令数量，并发送给所述指令调度单元; 确定在每个周期获得指令数量之后，如果发出到指令调度单元的每个周期的指令数量小于阈值水平，然后确定是否发出至少两个指令发送到指令调度单元 只有当每个周期的指令小于阈值水平时，它们彼此独立; 确定发出到指令调度单元的指令中的至少两个是否彼此独立; 以及当指令彼此独立而不引起显着的性能损失时，直到指令调度单元中的问题队列填充有指令数据，门控微处理器将来自状态机的信号关闭到空闲宏的电源。