公开(公告)号：US5796888A

公开(公告)日：1998-08-18

申请号：US718712

申请日：1996-09-24

申请人： Tohru Furukawa ,  Yoshikazu Nomura ,  Hiroshi Furukawa ,  Naoki Nakao ,  Nobuo Tomita

发明人： Tohru Furukawa ,  Yoshikazu Nomura ,  Hiroshi Furukawa ,  Naoki Nakao ,  Nobuo Tomita

IPC分类号： G02B6/38 ,  G02B6/35 ,  G02B6/36 ,  G02B26/08

CPC分类号： G02B6/3508 ,  G02B6/3548 ,  G02B6/358 ,  G02B6/3636 ,  G02B6/3652

摘要： According to the present invention, an optical switch apparatus is provided for switching the connections between a plurality of fixed optical fibers which are fixed and arranged on an optical fiber support base within a container filled with an index-of-refraction matching agent, and movable optical fibers provided on a movable base which is moved by a moving mechanism comprising a worm gear within the aforementioned container. In addition, a worm gear driving member and a cam driving member of a matching device are both provided on the exterior of the aforementioned container via a seal. This worm gear driving member which is connected to a control device, starts the positioning sequence and moves the movable base to a standby position following return of the movable base to a predetermined origin within the container. As a result, it is possible to prevent contamination of the index-of-refraction matching agent over a long period of time, and thereby reduce the connection loss to a satisfactory level. In addition, since the driving precision of the movable base is also improved, it is possible to achieve superior effects such as reduction of the array pitch of the fixed optical fibers, improvement of the precision and increase in the multiplicity of the optical switch apparatus.

摘要翻译： 根据本发明，提供一种光开关装置，用于切换多个固定光纤之间的连接，固定光纤被固定并布置在填充有折射率匹配剂的容器内的光纤支撑基座上，并且可移动 设置在由上述容器内的由蜗轮构成的移动机构移动的可动基座上的光纤。 此外，蜗杆传动构件和匹配装置的凸轮驱动构件均经由密封件设置在上述容器的外部。 连接到控制装置的该蜗轮传动构件开始定位顺序，并且在可移动底座返回到容器内的预定原点之前将可动基座移动到待机位置。 结果，可以防止长时间的折射率匹配剂的污染，从而将连接损失降低到令人满意的水平。 此外，由于可移动基座的驱动精度也提高，所以可以实现降低固定光纤的阵列间距，提高精度和提高光开关装置的多重性等优异的效果。

公开(公告)号：US20150036134A1

公开(公告)日：2015-02-05

申请号：US14447868

申请日：2014-07-31

申请人： Takanori Saitoh ,  Hiroshi Furukawa

发明人： Takanori Saitoh ,  Hiroshi Furukawa

IPC分类号： G01N21/25 ,  G02B6/293

CPC分类号： G01N21/255 ,  G01B11/16 ,  G01D5/35316 ,  G01D5/35387 ,  G01D5/3539 ,  G01K11/3206 ,  G01L1/246 ,  G01N2201/08 ,  G02B6/2932

摘要： A physical quantity measuring system includes an optical source which emits a measurement light to fiber Bragg grating (FBG) lines containing FBGs connected in cascade by an optical fiber, an optical switch including a common port for receiving the measurement light from the optical source, and input/output ports connected to the FBG lines, the optical switch outputting the measurement light, from the common port to each of the input/output ports at different time points, a wavelength separator which receives light reflected from the respective FBGs of the FBG lines, and separating the reflected light into a plurality of component lights having predetermined wavelengths, after the measurement light is output from the input/output ports, and optical receivers which receives the component lights from the wavelength separator and detects light intensities of the component lights.

摘要翻译： 物理量测量系统包括：光源，其向包含由光纤串联连接的FBG的光纤布拉格光栅（FBG）线发射测量光;光开关，包括用于接收来自光源的测量光的公共端口;以及 连接到FBG线的输入/输出端口，光学开关将不同时间点的公共端口从公共端口输出到每个输入/输出端口;波长分离器，其接收从FBG线的各个FBG反射的光 并且在从输入/输出端口输出测量光和从波长分离器接收分量光的光接收器之后，将反射光分离成具有预定波长的多个分量光，并检测分量光的光强度。

公开(公告)号：US08480314B2

公开(公告)日：2013-07-09

申请号：US12965377

申请日：2010-12-10

申请人： Daigo Saito ,  Kazuhiro Takizawa ,  Hiroshi Furukawa ,  Serin Khee Yen Tan ,  Quang Minh Ngo

发明人： Daigo Saito ,  Kazuhiro Takizawa ,  Hiroshi Furukawa ,  Serin Khee Yen Tan ,  Quang Minh Ngo

IPC分类号： G02B6/255

CPC分类号： G02B6/3846 ,  G02B6/262 ,  G02B6/3862 ,  G02B6/3898

摘要： A method of butting and connecting a first optical fiber and a second optical fiber in an optical connector comprises placing said optical connector that holds said first optical fiber in wherein an optical fiber connection tool; mounting said optical fiber holder on a holder mounting base of a front end bevel processing tool; processing a front end face of said second optical fiber such that said front end face of said second optical fiber is beveled relative to the surface perpendicular to the optical fiber axis direction; transferring said optical fiber holder to said holder support base; and moving said optical fiber holder toward said optical connector along said guide part, and butting and connecting the beveled front end face of said second optical fiber to the front end face of said first optical fiber such that their bevel directions are aligned.

摘要翻译： 一种在光连接器中对接和连接第一光纤和第二光纤的方法包括将保持所述第一光纤的所述光连接器放置在其中的光纤连接工具; 将所述光纤保持器安装在前端斜面加工工具的保持器安装基座上; 处理所述第二光纤的前端面，使得所述第二光纤的所述前端面相对于垂直于所述光纤轴线方向的表面倾斜; 将所述光纤保持器传送到所述保持器支撑基座; 以及沿着所述引导部件将所述光纤保持器朝着所述光连接器移动，并且将所述第二光纤的斜面前端面对接并连接到所述第一光纤的前端面，使得它们的斜面方向对齐。

公开(公告)号：US08352533B2

公开(公告)日：2013-01-08

申请号：US12332673

申请日：2008-12-11

申请人： Hiroshi Furukawa

发明人： Hiroshi Furukawa

IPC分类号： G06F7/57

CPC分类号： G06F7/5443

摘要： There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks inputting data of a second bit width different from the first bit width and performing computation; a second network connected to outputs of the plurality of second logic blocks; and a third network connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner.

摘要翻译： 提供了一种半导体集成电路，包括：多个可重新配置的第一逻辑块，多个第一逻辑块输入第一位宽的数据并执行计算; 以动态可重新配置的方式连接所述多个第一逻辑块的第一网络; 多个第二逻辑块，输入与第一位宽不同的第二位宽的数据，并执行计算; 连接到所述多个第二逻辑块的输出的第二网络; 以及以动态可重新配置的方式将包括在第一逻辑块中的计算单元的进位位输出连接到包括在第二逻辑块中的计算单元的输入的第三网络。

公开(公告)号：US20120320781A1

公开(公告)日：2012-12-20

申请号：US13580816

申请日：2011-02-23

申请人： Hiroshi Furukawa ,  Guangri Jin

发明人： Hiroshi Furukawa ,  Guangri Jin

IPC分类号： H04W40/02 ,  H04W24/00

CPC分类号： H04W40/08 ,  H04W40/14 ,  H04W40/24 ,  Y02D70/142 ,  Y02D70/22 ,  Y02D70/324 ,  Y02D70/34

摘要： Provided are a communication system and the like capable of making a stable relay route even when a propagation channel is fluctuated by the fluctuation of RSSI. For making a tree-type communication route whose root is a core node, each slave node, after the reception of the latest reset routing packet from a node, judges if the transmission source node should be the parent of the tree-type structure based on the sequential average of the reception power of n routing packets received from the same transmission source node. As the reception power is log-normally distributed in general, an asymptotically stable relay route can be obtained, especially by using the sequential average.

摘要翻译： 即使当传播路径由于RSSI的波动而波动时，也能够进行稳定的中继路径的通信系统等。 为了制作其根为核心节点的树型通信路由，每个从节点在从节点接收到最新的重置路由分组后，根据以下情况判断传输源节点是否为树型结构的父节点 从同一发送源节点接收的n个路由分组的接收功率的顺序平均值。 由于接收功率一般是对数正态分布的，所以可以获得渐近稳定的中继路由，特别是通过使用顺序平均值。

公开(公告)号：US07734896B2

公开(公告)日：2010-06-08

申请号：US11390131

申请日：2006-03-28

申请人： Hiroshi Furukawa

发明人： Hiroshi Furukawa

IPC分类号： G06F15/76

CPC分类号： G06F15/8007

摘要： A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor network which connects them in an arbitrary state; and an inter-processor network which connects between processor elements in an arbitrary state. Based on configuration data, the intra-processor network is reconfigurable to a desired connection state, and further, based on the configuration data, the inter-processor network is reconfigurable to a desired connection state.

摘要翻译： 基于配置数据动态地转换任意计算状态的可重构集成电路装置包括多个处理器元件，每个处理器元件具有输入端子，输出端子，并行设置的多个运算单元， 其执行与时钟信号同步的计算处理和以任意状态连接它们的处理器内网络; 以及以任意状态连接处理器元件之间的处理器间网络。 基于配置数据，内部处理器网络可重新配置为期望的连接状态，并且此外，基于配置数据，处理器间网络可重新配置为期望的连接状态。

公开(公告)号：US07590081B2

公开(公告)日：2009-09-15

申请号：US11197336

申请日：2005-08-05

申请人： Hiroshi Furukawa ,  Morihisa Momona ,  Koichi Ebata

发明人： Hiroshi Furukawa ,  Morihisa Momona ,  Koichi Ebata

IPC分类号： H04B7/14 ,  H04J1/16

CPC分类号： H04L45/00 ,  H04B7/155 ,  H04W16/14 ,  H04W40/06 ,  H04W40/08 ,  H04W40/12 ,  H04W40/16 ,  H04W40/22 ,  H04W40/248 ,  H04W84/00 ,  H04W88/04 ,  Y02D70/1242 ,  Y02D70/22 ,  Y02D70/322 ,  Y02D70/324 ,  Y02D70/34 ,  Y02D70/39 ,  Y02D70/446

摘要： A radio network can select a route of minimum path loss among entire relay routes and can set the relay route so as to satisfactorily resist interference. The radio network has a core node connected to a wired network, relay nodes each relaying at least one of a down-link data packet transmitted from the core node and an up-link data packet directed toward the core node, and a terminal station capable of transmission and reception of data packets with both the core node and the relay node. The relay node has total path loss optimized to be minimum between relay nodes included in a relay route of the data packet or between the relay node and the core node or both.

摘要翻译： 无线网络可以在整个中继路由中选择最小路径损耗的路由，并且可以设置中继路由以令人满意地抵抗干扰。 无线网络具有连接到有线网络的核心节点，每个中继从核心节点发送的下行链路数据分组和指向核心节点的上行链路数据分组中的至少一个的中继节点，以及能够 与核心节点和中继节点同时发送和接收数据包。 中继节点具有在数据分组的中继路由中包含的中继节点之间或中继节点与核心节点之间或两者之间优化为最小的总路径损耗。

公开(公告)号：US07554936B2

公开(公告)日：2009-06-30

申请号：US11214985

申请日：2005-08-31

申请人： Hiroshi Furukawa ,  Morihisa Momona ,  Koichi Ebata

发明人： Hiroshi Furukawa ,  Morihisa Momona ,  Koichi Ebata

IPC分类号： H04J3/08 ,  H04L12/56

CPC分类号： H04L45/00 ,  H04B7/155 ,  H04W16/14 ,  H04W40/06 ,  H04W40/08 ,  H04W40/12 ,  H04W40/16 ,  H04W40/22 ,  H04W40/248 ,  H04W84/00 ,  H04W88/04 ,  Y02D70/1242 ,  Y02D70/22 ,  Y02D70/322 ,  Y02D70/324 ,  Y02D70/34 ,  Y02D70/39 ,  Y02D70/446

摘要： A radio network can select a route of minimum path loss among entire relay routes and can set the relay route so as to satisfactorily resist interference. The radio network has a core node connected to a wired network, relay nodes each relaying at least one of a down-link data packet transmitted from the core node and an up-link data packet directed toward the core node, and a terminal station capable of transmission and reception of data packets with both the core node and the relay node. The relay node has total path loss optimized to be minimum between relay nodes included in a relay route of the data packet or between the relay node and the core node or both.

公开(公告)号：US07452138B2

公开(公告)日：2008-11-18

申请号：US11527564

申请日：2006-09-27

申请人： Daigo Saito ,  Kazuhiro Takizawa ,  Hiroshi Furukawa ,  Kenichi Nakazawa ,  Tsunetaka Ema ,  Kouji Shibata

发明人： Daigo Saito ,  Kazuhiro Takizawa ,  Hiroshi Furukawa ,  Kenichi Nakazawa ,  Tsunetaka Ema ,  Kouji Shibata

IPC分类号： G02B6/36

CPC分类号： G02B6/3846

摘要： An optical connector includes a connector body that has a first optical fiber housed in advance in a ferrule so as to project from a back end of the ferrule opposite to the connecting end surface and an anchoring fixture that anchors a second optical fiber that is to be optically connected to the first optical fiber, and by pressing the anchoring fixture into the connector body while the second optical fiber is anchored in this anchoring fixture, the anchoring fixture and the connector body are connected to optically connect the first optical fiber and the second optical fiber, and the connecting portion that connects the anchoring fixture and the connector body form a movable connecting portion that is adapted to vary the direction of the anchoring fixture with respect to the connector body.

公开(公告)号：US20080205582A1

公开(公告)日：2008-08-28

申请号：US12033969

申请日：2008-02-20

申请人： Hiroshi Furukawa

发明人： Hiroshi Furukawa

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  H03K19/17728

摘要： A processing element includes a shift register including n stages of registers mutually connected in series. Data held among the n stages of registers is rotated in synchronization with a clock signal. A number-of-stages determining circuit determines the number of stages to be used among the n stages of registers. An output terminal of the register in the last stage connects to an input terminal of the register in the first stage.

摘要翻译： 一种处理元件包括一个移位寄存器，它包括串联相互连接的n级寄存器。 在n个寄存器之间保存的数据与时钟信号同步旋转。 级数确定电路确定在n级寄存器中要使用的级数。 最后一级寄存器的输出端子连接到第一级寄存器的输入端。