公开(公告)号：US20250105015A1

公开(公告)日：2025-03-27

申请号：US18373080

申请日：2023-09-26

Applicant: Tokyo Electron Limited

Inventor： Shihsheng CHANG ,  Yen-Tien LU ,  Du ZHANG ,  Kai-Hung YU ,  David L O'MEARA

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/033

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method may include forming a first hardmask layer over a substrate. The method may include forming a second hardmask layer over the first hardmask layer. The method may include transferring a pattern from the second hardmask layer to the first hardmask layer, wherein the pattern in the first hardmask layer comprises a plurality of protruding structures, and each of the plurality of protruding structures has respective portions of its two sidewalls extending toward each other. The method may include depositing a modification layer extending along at least the respective portions of the sidewalls of each of the protruding structures. The method may include etching the substrate with the protruding structures and the modification layer both serving as a mask.

公开(公告)号：US20240395557A1

公开(公告)日：2024-11-28

申请号：US18322502

申请日：2023-05-23

Applicant: Tokyo Electron Limited

Inventor： Du ZHANG ,  Scott LEFEVRE ,  Jeffrey SHEARER ,  Peter BIOLSI

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/768

Abstract: A method is provided. The method includes etching a substrate to form a recess in the substrate through a plurality of stages. A first one of the plurality of stages forms an inhibitor layer lining an initial portion of the recess based on first etchant radicals. A second one of the plurality of stages exposes the initial portion of the recess based on ions. A third one of the plurality of stages extends the initial portion of the recess based on second etchant radicals.