公开(公告)号：US20220359718A1

公开(公告)日：2022-11-10

申请号：US17721551

申请日：2022-04-15

Applicant: Tokyo Electron Limited

Inventor： Yun HAN ,  Eric Chih-Fang LIU ,  Kai-Hung YU ,  Shihsheng CHANG ,  Alok RANJAN

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/311

Abstract: A method including providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate, each of the source/drain contact regions being recessed within a respective opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the opening and adjacent metal gate stacks provide sidewalls, and a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric from each opening down to a first depth, and a sacrificial gate capping layer is formed on the substrate while leaving each of the openings uncovered. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric from each opening down to a second depth.

公开(公告)号：US20210082750A1

公开(公告)日：2021-03-18

申请号：US17021586

申请日：2020-09-15

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung YU ,  Jodi GRZESKOWIAK ,  Nicholas JOY ,  Jeffrey SMITH

IPC: H01L21/768

Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.

公开(公告)号：US20210125863A1

公开(公告)日：2021-04-29

申请号：US17140310

申请日：2021-01-04

Applicant: Tokyo Electron Limited

Inventor： Robert CLARK ,  Kandabara TAPILY ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418

Abstract: A method of preparing a self-aligned via on a semiconductor workpiece includes using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules. The integrated sequence of processing steps include receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface; selectively etching the metal features to form a recess pattern by recessing the exposed surfaces of the metal features beneath the exposed surfaces of the dielectric layer using one of the one or more etching modules; and depositing an etch stop layer over the recess pattern using one of the one or more film-forming modules.

公开(公告)号：US20180211870A1

公开(公告)日：2018-07-26

申请号：US15875442

申请日：2018-01-19

Applicant: Tokyo Electron Limited

Inventor： Soo Doo CHAE ,  Jeffrey SMITH ,  Gerrit J. LEUSINK ,  Robert D. CLARK ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L23/522

Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

公开(公告)号：US20250105015A1

公开(公告)日：2025-03-27

申请号：US18373080

申请日：2023-09-26

Applicant: Tokyo Electron Limited

Inventor： Shihsheng CHANG ,  Yen-Tien LU ,  Du ZHANG ,  Kai-Hung YU ,  David L O'MEARA

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/033

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method may include forming a first hardmask layer over a substrate. The method may include forming a second hardmask layer over the first hardmask layer. The method may include transferring a pattern from the second hardmask layer to the first hardmask layer, wherein the pattern in the first hardmask layer comprises a plurality of protruding structures, and each of the plurality of protruding structures has respective portions of its two sidewalls extending toward each other. The method may include depositing a modification layer extending along at least the respective portions of the sidewalls of each of the protruding structures. The method may include etching the substrate with the protruding structures and the modification layer both serving as a mask.

公开(公告)号：US20210118730A1

公开(公告)日：2021-04-22

申请号：US17135136

申请日：2020-12-28

Applicant: Tokyo Electron Limited

Inventor： Robert CLARK ,  Kndabara TAPILY ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418

Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

公开(公告)号：US20160163591A1

公开(公告)日：2016-06-09

申请号：US14561331

申请日：2014-12-05

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro ISHIZAKA ,  Takashi SAKUMA ,  Osamu YOKOYAMA ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L23/532 ,  C23C14/34 ,  C23C16/52 ,  C23C14/24 ,  C23C14/54 ,  H01L21/285 ,  H01L23/528

CPC classification number: C23C14/34 ,  C23C14/046 ,  C23C14/165 ,  C23C14/24 ,  C23C14/54 ,  C23C16/52 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76846 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A Cu wiring forming method of forming Cu wiring that is to be arranged in contact with tungsten wiring, by filling Cu into a recess formed in a substrate, includes: removing a tungsten oxide formed on a surface of the tungsten wiring; forming a nitriding preventing film at least on the surface of the tungsten wiring in the recess; forming a barrier film that prevents diffusion of Cu, on a surface in the recess from above the nitriding preventing film; forming a liner film on the barrier film; and filling a Cu film on the liner film.

Abstract translation: 通过将Cu填充到形成在基板中的凹部中，形成与钨布线接触而布置的Cu布线的Cu布线形成方法包括：去除形成在钨布线的表面上的氧化钨; 至少在所述凹部中的所述钨线的表面上形成防氮膜; 形成阻止膜从氮化防止膜上方阻止在凹部的表面上的扩散的阻挡膜; 在阻挡膜上形成衬垫膜; 并在衬膜上填充Cu膜。

公开(公告)号：US20240304500A1

公开(公告)日：2024-09-12

申请号：US18178665

申请日：2023-03-06

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang LIU ,  Subhadeep KAL ,  Kai-Hung YU ,  Shihsheng CHANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823864 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/66545

Abstract: Aspects of the present disclosure provide a method for fabricating a forksheet semiconductor structure. For example, the method can include forming on a substrate a multi-layer stack including first and second semiconductor layers stacked over one another alternately, forming a cap layer over the multi-layer stack, forming a mandrel structure from the multi-layer stack and the cap layer, forming a fill material that surrounds the mandrel structure and has a top surface level with a top of the mandrel structure, partially recessing the cap layer to uncover opposite inner sidewalls of the fill material, forming sidewall spacers on the opposite inner sidewalls, directionally etching the multi-layer stack to define an insulation wall trench using the sidewall spacers as an etch mask, and forming an insulation material within the insulation wall trench to form an insulation wall that separates the multi-layer stack into insulated first and second multi-layer stacks.

公开(公告)号：US20200006129A1

公开(公告)日：2020-01-02

申请号：US16562207

申请日：2019-09-05

Applicant: Tokyo Electron Limited

Inventor： Soo Doo CHAE ,  Jeffrey SMITH ,  Gerrit J. LEUSINK ,  Robert D. CLARK ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L23/522

Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

公开(公告)号：US20190198390A1

公开(公告)日：2019-06-27

申请号：US15850458

申请日：2017-12-21

Applicant: Tokyo Electron Limited

Inventor： Takeshi ITATANI ,  Tadahiro ISHIZAKA ,  Kandabara TAPILY ,  Kai-Hung YU ,  Wanjae PARK

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/687 ,  H01L21/02

Abstract: A removal method is provided for selectively removing a plurality of types of metal oxide films in a plurality of recesses formed in a substrate that is arranged in a processing chamber. The removal method includes repeatedly performing process steps of exposing the plurality of types of metal oxide films to BCl3 gas or a BCl3 gas plasma generated by introducing BCl3 gas, stopping introduction of the BCl3 gas and performing a purge process, exposing the plurality of types of metal oxide films and/or a plurality of types of metal films underneath the metal oxide films to one or more different plasmas, at least one of which is generated by introducing a single gas of an inert gas, and stopping introduction of the inert gas and performing the purge process.