公开(公告)号：US20200006129A1

公开(公告)日：2020-01-02

申请号：US16562207

申请日：2019-09-05

Applicant: Tokyo Electron Limited

Inventor： Soo Doo CHAE ,  Jeffrey SMITH ,  Gerrit J. LEUSINK ,  Robert D. CLARK ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L23/522

Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

公开(公告)号：US20210028169A1

公开(公告)日：2021-01-28

申请号：US17039307

申请日：2020-09-30

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara N. TAPILY ,  Subhadeep KAL ,  Gerrit J. LEUSINK

IPC: H01L27/092 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L21/28 ,  H01L29/786 ,  H01L27/12

Abstract: Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.

公开(公告)号：US20180211870A1

公开(公告)日：2018-07-26

申请号：US15875442

申请日：2018-01-19

Applicant: Tokyo Electron Limited

Inventor： Soo Doo CHAE ,  Jeffrey SMITH ,  Gerrit J. LEUSINK ,  Robert D. CLARK ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L23/522

Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.