公开(公告)号：US20240234158A1

公开(公告)日：2024-07-11

申请号：US18151223

申请日：2023-01-06

Applicant: Tokyo Electron Limited

Inventor： Indroneil Roy ,  Jason Marion ,  Yusuke Yoshida ,  Yun Han ,  Aelan Mosden ,  Ken Kobayashi

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/30655 ,  H01J37/32816 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31144 ,  H01J2237/3345 ,  H01J2237/3347

Abstract: A method for fabricating a semiconductor device includes forming a pattern of trenches by etching a first layer formed over an underlying layer of a substrate, each of the trenches having an aspect ratio (AR) in a range with a lower limit of a first AR and an upper limit of a second AR, the pattern including a low-AR trench having the first AR and a high-AR trench having the second AR, the AR of a trench being a ratio of its depth to its opening width, the etching including: executing a first recipe in a plasma chamber to anisotropically etch the first layer for a first duration by flowing etchants through the chamber, an etch rate of the first layer being higher on the low-AR trench relative to that on the high-AR trench; and after executing the first recipe, executing a second recipe in the plasma chamber to etch the first layer anisotropically and concurrently deposit oxygen-containing etch byproducts to passivate exposed portions of sides of the trenches, the etch rate of the first layer being lower on the low-AR trench relative to that on the high-AR trench, wherein executing the second recipe increases a relative oxygen content in the plasma chamber from a first value during the executing of the first recipe to a second value.