公开(公告)号：US20250046617A1

公开(公告)日：2025-02-06

申请号：US18362608

申请日：2023-07-31

Applicant: Tokyo Electron Limited

Inventor： Adam Pranda ,  Yusuke Yoshida ,  Aelan Mosden ,  Yun Han

IPC: H01L21/311 ,  H01J37/32 ,  H01L29/66

Abstract: A method of processing a substrate that includes: forming a bottom passivation layer including an oxide over a first portion of a dielectric layer at a bottom of a recess of the substrate, the recess having sidewalls including a second portion of the dielectric layer; and performing a lateral etch to etch the second portion of the dielectric layer, the bottom passivation layer covering the first portion of the dielectric layer during the lateral etch, and where the forming of the bottom passivation layer includes exposing the substrate to a first plasma including a halogen, and exposing the substrate to a second plasma including oxygen to form the bottom passivation layer.

公开(公告)号：US20240234158A1

公开(公告)日：2024-07-11

申请号：US18151223

申请日：2023-01-06

Applicant: Tokyo Electron Limited

Inventor： Indroneil Roy ,  Jason Marion ,  Yusuke Yoshida ,  Yun Han ,  Aelan Mosden ,  Ken Kobayashi

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/30655 ,  H01J37/32816 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31144 ,  H01J2237/3345 ,  H01J2237/3347

Abstract: A method for fabricating a semiconductor device includes forming a pattern of trenches by etching a first layer formed over an underlying layer of a substrate, each of the trenches having an aspect ratio (AR) in a range with a lower limit of a first AR and an upper limit of a second AR, the pattern including a low-AR trench having the first AR and a high-AR trench having the second AR, the AR of a trench being a ratio of its depth to its opening width, the etching including: executing a first recipe in a plasma chamber to anisotropically etch the first layer for a first duration by flowing etchants through the chamber, an etch rate of the first layer being higher on the low-AR trench relative to that on the high-AR trench; and after executing the first recipe, executing a second recipe in the plasma chamber to etch the first layer anisotropically and concurrently deposit oxygen-containing etch byproducts to passivate exposed portions of sides of the trenches, the etch rate of the first layer being lower on the low-AR trench relative to that on the high-AR trench, wherein executing the second recipe increases a relative oxygen content in the plasma chamber from a first value during the executing of the first recipe to a second value.

公开(公告)号：US11715643B2

公开(公告)日：2023-08-01

申请号：US16890141

申请日：2020-06-02

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Daisuke Ito ,  Matthew Flaugh ,  Yusuke Muraki ,  Aelan Mosden

IPC: H01L21/3213 ,  C23F1/12 ,  C23F1/02 ,  H01L21/66 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/32135 ,  C23F1/02 ,  C23F1/12 ,  H01L21/30621 ,  H01L21/32136 ,  H01L21/32138 ,  H01L22/12 ,  H01L21/0228

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.

公开(公告)号：US11322350B2

公开(公告)日：2022-05-03

申请号：US16868277

申请日：2020-05-06

Applicant: Tokyo Electron Limited

Inventor： Daisuke Ito ,  Subhadeep Kal ,  Shinji Irie ,  Aelan Mosden

IPC: H01L21/3065 ,  H01L21/027 ,  H01J37/32 ,  H01L21/67 ,  G03F7/20

Abstract: Embodiments provide a non-plasma etch, such as a gas-phase and/or remote plasma etch, of titanium-containing material layers with tunable selectivity to other material layers. A substrate is received within a process chamber, and the substrate has exposed material layers including a titanium-containing material layer and at least one additional material layer. The additional material layer is selectively etched with respect to the titanium-containing material layer by exposing the substrate to a controlled environment including a halogen-containing gas. For one embodiment, the halogen-containing gas includes a fluorine-based gas. For one embodiment, the titanium-containing material layer is a titanium or a titanium nitride material layer. For one embodiment, the additional material layer includes tungsten, tungsten oxide, hafnium oxide, silicon oxide, silicon-germanium, silicon, silicon nitride, and/or aluminum oxide. A non-selective etch with respect to the titanium-containing material layer can be performed by modulating the process parameters such as temperature.

公开(公告)号：US09748110B2

公开(公告)日：2017-08-29

申请号：US15247138

申请日：2016-08-25

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Angelique D. Raley ,  Nihar Mohanty ,  Aelan Mosden

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a conformal spacer deposition using an oxide, the deposition creating a conformal layer; performing a spacer RIE process and a pull process, thereby generating a second spacer pattern, the spacer RIE process includes adsorption of N-containing gas on a surface of the substrate which activates the surface to react with an F- and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.

公开(公告)号：US20160379842A1

公开(公告)日：2016-12-29

申请号：US15191956

申请日：2016-06-24

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

CPC classification number: H01L21/31116 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/67248

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

Abstract translation: 描述了用于干燥去除微电子工件上的材料的方法。 该方法包括接收具有暴露由硅构成的目标层的表面和（1）有机材料或（2）氧和氮两者的表面的工件，并且从工件中选择性地去除目标层的至少一部分。 选择性去除包括将工件的表面暴露于含有N，H和F的化学环境处于第一设定点温度以化学改变目标层的表面区域，然后将工件的温度升高到第二设定点 温度以去除目标层的化学处理的表面区域。

公开(公告)号：US11538691B2

公开(公告)日：2022-12-27

申请号：US17219413

申请日：2021-03-31

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

公开(公告)号：US11482423B2

公开(公告)日：2022-10-25

申请号：US17161199

申请日：2021-01-28

Applicant: Tokyo Electron Limited

Inventor： Pingshan Luan ,  Aelan Mosden

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311

Abstract: In certain embodiments, a method for processing a semiconductor substrate includes receiving a semiconductor substrate that includes a film stack. The film stack includes first and second germanium-containing layers and a first silicon layer positioned between the first and second germanium-containing layers. The method includes selectively etching the first silicon layer by exposing the film stack to a plasma that includes fluorine agents and nitrogen agents. The plasma etches the first silicon layer, and causes a passivation layer to be formed on exposed surfaces of the first and second germanium-containing layers to inhibit etching of the first and second germanium-containing layers during exposure of the film stack to the plasma.

公开(公告)号：US11380554B2

公开(公告)日：2022-07-05

申请号：US16787867

申请日：2020-02-11

Applicant: TOKYO ELECTRON LIMITED

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/311

Abstract: A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.

公开(公告)号：US11189499B2

公开(公告)日：2021-11-30

申请号：US16802554

申请日：2020-02-27

Applicant: Tokyo Electron Limited

Inventor： Yu-Hao Tsai ,  Du Zhang ,  Mingmei Wang ,  Aelan Mosden ,  Matthew Flaugh

IPC: H01L21/3213

Abstract: Methods for the atomic layer etch (ALE) of tungsten or other metal layers are disclosed that use in part sequential oxidation and reduction of tungsten/metal layers to achieve target etch parameters. For one embodiment, a metal layer is first oxidized to form a metal oxide layer and an underlying metal layer. The metal oxide layer is then reduced to form a surface metal layer and an underlying metal oxide layer. The surface metal layer is then removed to leave the underlying metal oxide layer and the underlying metal layer. Further, the oxidizing, reducing, and removing processes can be repeated to achieve a target etch depth. In addition, a target etch rate can also achieved for each process cycle of oxidizing, reducing, and removing.