公开(公告)号：US20180233407A1

公开(公告)日：2018-08-16

申请号：US15895736

申请日：2018-02-13

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Sangcheol Han ,  Soo Doo Chae

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02263 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/28562 ,  H01L21/3105 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53295

Abstract: A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.

公开(公告)号：US10453749B2

公开(公告)日：2019-10-22

申请号：US15895736

申请日：2018-02-13

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Sangcheol Han ,  Soo Doo Chae

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/532

Abstract: A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.

公开(公告)号：US10916561B2

公开(公告)日：2021-02-09

申请号：US16374450

申请日：2019-04-03

Applicant: Tokyo Electron Limited

Inventor： Karthik Pillai ,  Soo Doo Chae ,  Sangcheol Han

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/28

Abstract: A method is provided for forming a semiconductor device. The method includes forming a vertical film stack containing a sacrificial layer on a substrate and dielectric layers alternatingly and repeatedly stacked on the sacrificial layer, removing the sacrificial layer to form a horizontal channel above the substrate, depositing a conformal dielectric layer in the horizontal channel, etching trenches in the vertical film stack that connect to the horizontal channel. The method further includes removing the conformal dielectric layer from the horizontal channel, filling the horizontal channel and the trenches with a first electrically conductive material, removing the first electrically conductive material from the trenches, and filling the trenches with a second electrically conductive material.

公开(公告)号：US20190304995A1

公开(公告)日：2019-10-03

申请号：US16374450

申请日：2019-04-03

Applicant: Tokyo Electron Limited

Inventor： Karthik Pillai ,  Soo Doo Chae ,  Sangcheol Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

Abstract: A method is provided for forming a semiconductor device. The method includes forming a vertical film stack containing a sacrificial layer on a substrate and dielectric layers alternatingly and repeatedly stacked on the sacrificial layer, removing the sacrificial layer to form a horizontal channel above the substrate, depositing a conformal dielectric layer in the horizontal channel, etching trenches in the vertical film stack that connect to the horizontal channel. The method further includes removing the conformal dielectric layer from the horizontal channel, filling the horizontal channel and the trenches with a first electrically conductive material, removing the first electrically conductive material from the trenches, and filling the trenches with a second electrically conductive material.