公开(公告)号：US10861739B2

公开(公告)日：2020-12-08

申请号：US16440679

申请日：2019-06-13

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/324 ,  H01L21/02

Abstract: A process is provided in which low-k layers are protected from damage by the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to replace organic layers that typically require ashing processes to remove. By removing the need for certain ashing steps, the exposure of the low-k dielectric layer to ashing processes may be lessened. In another embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material before a subsequent process step that may damage the low-k layer is performed. The thermal decomposition materials may be removed by a thermal anneal process step that does not damage the low-k layers.

公开(公告)号：US20190393084A1

公开(公告)日：2019-12-26

申请号：US16446572

申请日：2019-06-19

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/768 ,  H01L21/311

Abstract: A process is provided in which low-k layers are protected from damage caused by exposure to atmospheric conditions by providing protection through the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to coat exposed regions of the low-k layers so that the low-k layers are not exposed to atmospheric conditions. In an exemplary embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material. In another exemplary embodiment, trench and via openings in the low-k layer are plugged with the thermal decomposition material. The thermal decomposition materials may be removed by a heat based thermal anneal process step that does not damage the low-k layers.

公开(公告)号：US20190385903A1

公开(公告)日：2019-12-19

申请号：US16440679

申请日：2019-06-13

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/324 ,  H01L21/02

Abstract: A process is provided in which low-k layers are protected from damage by the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to replace organic layers that typically require ashing processes to remove. By removing the need for certain ashing steps, the exposure of the low-k dielectric layer to ashing processes may be lessened. In another embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material before a subsequent process step that may damage the low-k layer is performed. The thermal decomposition materials may be removed by a thermal anneal process step that does not damage the low-k layers.

公开(公告)号：US10950442B2

公开(公告)日：2021-03-16

申请号：US16460575

申请日：2019-07-02

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/02

Abstract: Embodiments are disclosed that improve etch uniformity during multi-patterning processes for the manufacture of microelectronic workpieces by reshaping spacers using thermal decomposition materials as a protective layer. Because the thermal decomposition material can be removed through thermal treatment processes without requiring etch processes, spacers can be reshaped with no spacer profile change or damage while suppressing undesired gouging differences in underlying layers and related degradation in etch uniformity.

公开(公告)号：US10886176B2

公开(公告)日：2021-01-05

申请号：US16374239

申请日：2019-04-03

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Kaoru Maekawa

IPC: H01L21/768

Abstract: Self-aligned interconnect patterning for back-end-of-line (BEOL) structures is described. A method of fabricating an interconnect structure for an integrated circuit includes depositing a first metal layer on an initial interconnect structure, forming a patterned spacer layer containing recessed features on the first metal layer, and etching a self-aligned via in the first metal layer and into the initial interconnect structure using a recessed feature in the patterned spacer layer as a mask. The method further includes filling the via in the first metal layer and the recessed features in the patterned spacer layer with a second metal layer, removing the patterned spacer layer, and etching a recessed feature in the first metal layer using the second metal layer as a mask.

公开(公告)号：US20200013619A1

公开(公告)日：2020-01-09

申请号：US16460575

申请日：2019-07-02

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: Embodiments are disclosed that improve etch uniformity during multi-patterning processes for the manufacture of microelectronic workpieces by reshaping spacers using thermal decomposition materials as a protective layer. Because the thermal decomposition material can be removed through thermal treatment processes without requiring etch processes, spacers can be reshaped with no spacer profile change or damage while suppressing undesired gouging differences in underlying layers and related degradation in etch uniformity.

公开(公告)号：US10978300B2

公开(公告)日：2021-04-13

申请号：US16507821

申请日：2019-07-10

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

Abstract: Embodiments are disclosed that reduce gouging during multi-patterning processes using thermal decomposition materials. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as cores during multiple patterning processes. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as a gap fill material during multiple patterning processes. By using thermal decomposition material, gouging of an underlying layer, such as a hard mask layer, can be reduced or suppressed for patterned structures being formed using the self-aligned multi-patterning processes because more destructive etch processes, such as plasma etch processes, are not required to remove the thermal decomposition materials.

公开(公告)号：US10916428B2

公开(公告)日：2021-02-09

申请号：US16290580

申请日：2019-03-01

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/033

Abstract: A process is provided in which a patterned layer, an intervening layer and a first layer to be etched according to the pattern of the patterned layer are formed. The intervening layer may be a thermal decomposition layer that may be removed by a heat based removal process. After etching the first layer, the use of a heat based removal process may allow the intervening layer to be removed from the substrate without altering the first layer. In one embodiment, the first layer may be a memorization layer and the process may be a multiple patterning process.

公开(公告)号：US20200020534A1

公开(公告)日：2020-01-16

申请号：US16290580

申请日：2019-03-01

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/033

Abstract: A process is provided in which a patterned layer, an intervening layer and a first layer to be etched according to the pattern of the patterned layer are formed. The intervening layer may be a thermal decomposition layer that may be removed by a heat based removal process. After etching the first layer, the use of a heat based removal process may allow the intervening layer to be removed from the substrate without altering the first layer. In one embodiment, the first layer may be a memorization layer and the process may be a multiple patterning process.

公开(公告)号：US20200020523A1

公开(公告)日：2020-01-16

申请号：US16507821

申请日：2019-07-10

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/02

Abstract: Embodiments are disclosed that reduce gouging during multi-patterning processes using thermal decomposition materials. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as cores during multiple patterning processes. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as a gap fill material during multiple patterning processes. By using thermal decomposition material, gouging of an underlying layer, such as a hard mask layer, can be reduced or suppressed for patterned structures being formed using the self-aligned multi-patterning processes because more destructive etch processes, such as plasma etch processes, are not required to remove the thermal decomposition materials.