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    Plasma treatment method to improve photo resist roughness and remove photo resist scum
    4.
    发明授权
    Plasma treatment method to improve photo resist roughness and remove photo resist scum 有权

    公开(公告)号：US11372332B2

    公开(公告)日：2022-06-28

    申请号：US16594951

    申请日：2019-10-07

    Applicant: Tokyo Electron Limited

    Inventor： Wan Jae Park ,  Akiteru Ko

    IPC: G03F7/42 ,  G03F7/20 ,  H01L21/027

    Abstract: A patterned photo resist layer (for example an EUV photo resist layer), which may exhibit line width roughness (LWR) and line edge roughness (LER) or scum is treated with a plasma treatment before subsequent etching processes. The plasma treatment reduces LWR, LER, and/or photo resist scum. In one exemplary embodiment, the plasma treatment may include a plasma formed using a gas having a boron and halogen compound. In one embodiment, the gas compound may be a boron and chlorine compound, for example boron trichloride (BCl3) gas. In another embodiment, the gas compound may be a boron and fluorine compound, for example BxFy gases. The plasma treatment process may modify the photoresist surface to improve LWR, LER, and scum effects by removing roughness from the photo resist surface and removing photo resist residues which may case scumming.

    METHOD FOR PITCH SPLIT PATTERNING USING SIDEWALL IMAGE TRANSFER
    5.
    发明申请
    METHOD FOR PITCH SPLIT PATTERNING USING SIDEWALL IMAGE TRANSFER 有权

    公开(公告)号：US20210407804A1

    公开(公告)日：2021-12-30

    申请号：US16916452

    申请日：2020-06-30

    Applicant: Tokyo Electron Limited

    Inventor： Akiteru Ko ,  Richard Farrell

    IPC: H01L21/033 ,  G03F7/09 ,  G03F7/11 ,  G03F7/20 ,  G03F7/26 ,  H01L21/027

    Abstract: A method of forming a device includes forming a hard mask layer over an underlying layer of a substrate, forming an anti-reflective coating layer over the hard mask layer, forming a patterned resist layer over the anti-reflective coating layer, and forming a mandrel including the anti-reflective coating layer by patterning the anti-reflective coating layer using the patterned resist layer as an etch mask. The method includes forming a sidewall spacer on the mandrel including the anti-reflective coating layer, forming a freestanding spacer on the hard mask layer by removing the mandrel from the anti-reflective coating layer, and using the freestanding spacer as an etch mask, patterning the underlying layer of the substrate.

    METHODS TO REDUCE MICROBRIDGE DEFECTS IN EUV PATTERNING FOR MICROELECTRONIC WORKPIECES
    6.
    发明申请
    METHODS TO REDUCE MICROBRIDGE DEFECTS IN EUV PATTERNING FOR MICROELECTRONIC WORKPIECES 有权

    公开(公告)号：US20210305048A1

    公开(公告)日：2021-09-30

    申请号：US16827928

    申请日：2020-03-24

    Applicant: Tokyo Electron Limited

    Inventor： Akiteru Ko

    IPC: H01L21/033 ,  G02B1/11 ,  G02B1/14 ,  G03F7/20

    Abstract: Embodiments reduce or eliminate microbridge defects in extreme ultraviolet (EUV) patterning for microelectronic workpieces. A patterned layer is formed over a multilayer structure using an EUV patterning process. Protective material is then deposited over the patterned layer using one or more oblique deposition processes. One or more material bridges extending between line patterns within the patterned layer are then removed while using the protective material to protect the line patterns. As such, microbridge defects caused in prior solutions are reduced or eliminated. For one embodiment, the oblique deposition processes include physical vapor deposition (PVD) processes that apply the same or different protective materials in multiple directions with respect to line patterns within the patterned layer. For one embodiment, the removing includes one or more plasma trim processes. Variations can be implemented.

    METHODS FOR EUV INVERSE PATTERNING IN PROCESSING OF MICROELECTRONIC WORKPIECES
    7.
    发明申请
    METHODS FOR EUV INVERSE PATTERNING IN PROCESSING OF MICROELECTRONIC WORKPIECES 有权

    公开(公告)号：US20210296125A1

    公开(公告)日：2021-09-23

    申请号：US16824346

    申请日：2020-03-19

    Applicant: Tokyo Electron Limited

    Inventor： Eric Chih-Fang Liu ,  Akiteru Ko ,  Subhadeep Kal ,  Toshiharu Wada

    IPC: H01L21/033 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

    Abstract: Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.

    Multiple Patterning Processes
    8.
    发明申请
    Multiple Patterning Processes 有权

    公开(公告)号：US20210242020A1

    公开(公告)日：2021-08-05

    申请号：US16780248

    申请日：2020-02-03

    Applicant: Tokyo Electron Limited

    Inventor： David L. O'Meara ,  Eric Chih-Fang Liu ,  Jodi Grzeskowiak ,  Anton deVilliers ,  Akiteru Ko ,  Anthony Dip

    IPC: H01L21/033

    Abstract: A method of forming a device includes depositing a first etch mask layer over a mandrel formed using a lithography process. The method includes depositing a second etch mask layer over the first etch mask layer. The method includes, using a first anisotropic etching process, etching the first etch mask layer and the second etch mask layer to form an etch mask including the first etch mask layer and the second etch mask layer. The method includes removing the mandrel to expose an underlying surface of the layer to be patterned. The method includes, using the etch mask, forming a feature by performing a second anisotropic etching process to pattern the layer to be patterned, where during the first anisotropic etching process, the first etch mask layer etches at a first rate and the second etch mask layer etches at a second rate, and where the first rate is different from the second rate.

    Method of patterning low-k materials using thermal decomposition materials
    9.
    发明授权
    Method of patterning low-k materials using thermal decomposition materials 有权

    公开(公告)号：US10861739B2

    公开(公告)日：2020-12-08

    申请号：US16440679

    申请日：2019-06-13

    Applicant: Tokyo Electron Limited

    Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/324 ,  H01L21/02

    Abstract: A process is provided in which low-k layers are protected from damage by the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to replace organic layers that typically require ashing processes to remove. By removing the need for certain ashing steps, the exposure of the low-k dielectric layer to ashing processes may be lessened. In another embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material before a subsequent process step that may damage the low-k layer is performed. The thermal decomposition materials may be removed by a thermal anneal process step that does not damage the low-k layers.

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