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    Method and process using dual memorization layer for multi-color spacer patterning
    1.
    发明授权
    Method and process using dual memorization layer for multi-color spacer patterning 有权

    公开(公告)号：US11380579B2

    公开(公告)日：2022-07-05

    申请号：US16864472

    申请日：2020-05-01

    Applicant: Tokyo Electron Limited

    Inventor： Hirokazu Aizawa ,  Kaoru Maekawa ,  Akiteru Ko

    IPC: H01L21/768 ,  H01L23/532

    Abstract: A self-aligned multiple patterning (SAMP) multi-color spacer patterning process is disclosed for formation of structures on substrates. Trenches and vias may be formed in the process. A trench memorization layer and a via memorization layer may be formed on the substrate. In one embodiment, the trench memorization layer and the via memorization layer are formed between the multi-color spacer patterning structures and a low-k interlayer dielectric layer. The use of the trench memorization layer and the via memorization layer allows the formation of trenches and vias in the low-k interlayer dielectric layer without causing damage to the low-k properties of the low-k interlayer dielectric layer.

    Method and structure for low density silicon oxide for fusion bonding and debonding
    2.
    发明授权
    Method and structure for low density silicon oxide for fusion bonding and debonding 有权

    公开(公告)号：US11315789B2

    公开(公告)日：2022-04-26

    申请号：US16573775

    申请日：2019-09-17

    Applicant: Tokyo Electron Limited

    Inventor： Kiyotaka Imai ,  Hirokazu Aizawa ,  Hiroshi Maeda ,  Kaoru Maekawa ,  Yuji Mimura ,  Harunobu Suenaga

    IPC: H01L21/20 ,  H01L21/50

    Abstract: Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

    SEMICONDUCTOR BACK END OF LINE (BEOL) INTERCONNECT USING MULTIPLE MATERIALS IN A FULLY SELF-ALIGNED VIA (FSAV) PROCESS
    3.
    发明申请
    SEMICONDUCTOR BACK END OF LINE (BEOL) INTERCONNECT USING MULTIPLE MATERIALS IN A FULLY SELF-ALIGNED VIA (FSAV) PROCESS 审中-公开

    公开(公告)号：US20200303253A1

    公开(公告)日：2020-09-24

    申请号：US16356434

    申请日：2019-03-18

    Applicant: Tokyo Electron Limited

    Inventor： Hirokazu Aizawa ,  Kaoru Maekawa

    IPC: H01L21/768 ,  H01L21/321

    Abstract: Embodiments of systems and methods for semiconductor back end of line (BEOL) interconnect using multiple materials in a fully self-aligned via (FSAV) process. In an embodiment, a method includes receiving a substrate with a patterned structure formed on a surface of the substrate. A method may also include depositing a first interconnect material in a first region of the patterned structure. Such methods may also include depositing a second interconnect material in a second region of the patterned structure, wherein the first interconnect material is different from the second interconnect material, and wherein the first region and the second region include a common layer of the patterned structures.

    Wrap-around contact integration scheme
    4.
    发明授权
    Wrap-around contact integration scheme 有权

    公开(公告)号：US10217670B2

    公开(公告)日：2019-02-26

    申请号：US15697249

    申请日：2017-09-06

    Applicant: Tokyo Electron Limited

    Inventor： Kandabara N. Tapily ,  Satoru Nakamura ,  Soo Doo Chae ,  Akiteru Ko ,  Kaoru Maekawa ,  Gerrit J. Leusink

    IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12

    Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

    Method of patterning low-k materials using thermal decomposition materials
    8.
    发明授权
    Method of patterning low-k materials using thermal decomposition materials 有权

    公开(公告)号：US10861739B2

    公开(公告)日：2020-12-08

    申请号：US16440679

    申请日：2019-06-13

    Applicant: Tokyo Electron Limited

    Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/324 ,  H01L21/02

    Abstract: A process is provided in which low-k layers are protected from damage by the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to replace organic layers that typically require ashing processes to remove. By removing the need for certain ashing steps, the exposure of the low-k dielectric layer to ashing processes may be lessened. In another embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material before a subsequent process step that may damage the low-k layer is performed. The thermal decomposition materials may be removed by a thermal anneal process step that does not damage the low-k layers.

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