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公开(公告)号：US20180211638A1
公开(公告)日：2018-07-26
申请号：US15415569
申请日：2017-01-25
申请人： Tolga Ozguner , Jeffrey Powers Bradford , Miguel Comparan , Gene Leung , Adam James Muff , Ryan Scott Haraden , Christopher Jon Johnson
发明人： Tolga Ozguner , Jeffrey Powers Bradford , Miguel Comparan , Gene Leung , Adam James Muff , Ryan Scott Haraden , Christopher Jon Johnson
CPC分类号： G09G5/395 , G02B27/0103 , G02B27/017 , G02B2027/014 , G02B2027/0178 , G02B2027/0187 , G03H1/0005 , G03H2001/0088 , G06F1/163 , G06F3/011 , G06F12/0207 , G06F12/0862 , G06F12/121 , G06F12/128 , G06F2212/1016 , G06F2212/1028 , G06F2212/1044 , G06F2212/455 , G06F2212/6026 , G06T1/20 , G06T1/60 , G09G3/003 , G09G2360/121 , Y02D10/13
摘要： Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.
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公开(公告)号：US08217953B2
公开(公告)日：2012-07-10
申请号：US12110045
申请日：2008-04-25
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译： 电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。 特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离 在各向异性过滤算法中使用各向异性。
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公开(公告)号：US07890699B2
公开(公告)日：2011-02-15
申请号：US11972221
申请日：2008-01-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0811
摘要： A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
摘要翻译： 在将所请求的数据返回到请求者的同时，在将所请求的数据缓存在较低级别的高速缓存中的同时，电路装置和方法将所请求的数据的存储绕过多层存储器体系结构的更高级缓存。 对于某些类型的数据，例如仅使用一次和/或很少被修改或写回存储器的数据，绕过较高级别高速缓存中的存储降低了请求的数据从较高级别投出常用数据的可能性 缓存。 然而，通过将数据缓存在较低级别的缓存中，低级缓存仍然可以窥探数据请求，并在数据已经缓存在较低级别缓存中的情况下返回请求的数据。
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公开(公告)号：US20090113181A1
公开(公告)日：2009-04-30
申请号：US11877754
申请日：2007-10-24
申请人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
发明人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
IPC分类号： G06F9/312
CPC分类号： G06F9/3885 , G06F9/3851
摘要： A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.
摘要翻译： 提供了一种用于在处理器中执行指令的方法和装置。 在本发明的一个实施例中，该方法包括接收多个指令。 多个指令包括第一线程中的第一指令和第二线程中的第二指令。 该方法还包括形成包括第一指令类型的指令和第二指令类型的指令的公共发行组。 该方法还包括向第一执行单元和第二执行单元发布公共问题组。 向第一执行单元发出第一指令类型的指令，并向第二执行单元发出第二指令类型的指令。
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公开(公告)号：US20120169755A1
公开(公告)日：2012-07-05
申请号：US13421169
申请日：2012-03-15
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译： 电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。 特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离 在各向异性过滤算法中使用各向异性。
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公开(公告)号：US08310497B2
公开(公告)日：2012-11-13
申请号：US13421169
申请日：2012-03-15
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
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公开(公告)号：US08082420B2
公开(公告)日：2011-12-20
申请号：US11877754
申请日：2007-10-24
申请人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
发明人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3851
摘要： A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.
摘要翻译： 提供了一种用于在处理器中执行指令的方法和装置。 在本发明的一个实施例中，该方法包括接收多个指令。 多个指令包括第一线程中的第一指令和第二线程中的第二指令。 该方法还包括形成包括第一指令类型的指令和第二指令类型的指令的公共发行组。 该方法还包括向第一执行单元和第二执行单元发布公共问题组。 向第一执行单元发出第一指令类型的指令，并向第二执行单元发出第二指令类型的指令。
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公开(公告)号：US20090315908A1
公开(公告)日：2009-12-24
申请号：US12110045
申请日：2008-04-25
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译： 电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。 特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离 在各向异性过滤算法中使用各向异性。
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公开(公告)号：US20090182944A1
公开(公告)日：2009-07-16
申请号：US11972221
申请日：2008-01-10
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0811
摘要： A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
摘要翻译： 在将所请求的数据返回到请求者的同时，在将所请求的数据缓存在较低级别的高速缓存中的同时，电路装置和方法将所请求的数据的存储绕过多层存储器体系结构的更高级缓存。 对于某些类型的数据，例如仅使用一次和/或很少被修改或写回存储器的数据，绕过较高级别高速缓存中的存储降低了请求的数据从较高级别投出常用数据的可能性 缓存。 然而，通过将数据缓存在较低级别的缓存中，低级缓存仍然可以窥探数据请求，并在数据已经缓存在较低级别缓存中的情况下返回请求的数据。
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10.发明申请公开(公告)号：US20130159799A1
公开(公告)日：2013-06-20
申请号：US13330921
申请日：2011-12-20
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/27 , G01R31/318566 , G06F11/2242
摘要： A method and circuit arrangement utilize scan logic disposed on a multi-core processor integrated circuit device or chip to perform internal voting-based built in self test (BIST) of the chip. Test patterns are generated internally on the chip and communicated to the scan chains within multiple processing cores on the chip. Test results output by the scan chains are compared with one another on the chip, and majority voting is used to identify outlier test results that are indicative of a faulty processing core. A bit position in a faulty test result may be used to identify a faulty latch in a scan chain and/or a faulty functional unit in the faulty processing core, and a faulty processing core and/or a faulty functional unit may be automatically disabled in response to the testing.
摘要翻译： 一种方法和电路装置利用设置在多核处理器集成电路器件或芯片上的扫描逻辑来执行基于内部投票的内置自检（BIST）芯片。 测试模式在芯片内部产生，并传送到芯片上多个处理核心内的扫描链。 扫描链输出的测试结果在芯片上相互比较，多数表决用于识别表示故障处理核心的异常值测试结果。 故障测试结果中的位位置可用于识别故障处理核心中的扫描链和/或故障功能单元中的故障锁存器，并且故障处理核心和/或故障功能单元可能被自动禁用 响应测试。
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