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公开(公告)号：US20180211638A1
公开(公告)日：2018-07-26
申请号：US15415569
申请日：2017-01-25
申请人： Tolga Ozguner , Jeffrey Powers Bradford , Miguel Comparan , Gene Leung , Adam James Muff , Ryan Scott Haraden , Christopher Jon Johnson
发明人： Tolga Ozguner , Jeffrey Powers Bradford , Miguel Comparan , Gene Leung , Adam James Muff , Ryan Scott Haraden , Christopher Jon Johnson
CPC分类号： G09G5/395 , G02B27/0103 , G02B27/017 , G02B2027/014 , G02B2027/0178 , G02B2027/0187 , G03H1/0005 , G03H2001/0088 , G06F1/163 , G06F3/011 , G06F12/0207 , G06F12/0862 , G06F12/121 , G06F12/128 , G06F2212/1016 , G06F2212/1028 , G06F2212/1044 , G06F2212/455 , G06F2212/6026 , G06T1/20 , G06T1/60 , G09G3/003 , G09G2360/121 , Y02D10/13
摘要： Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.
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公开(公告)号：US20160180493A1
公开(公告)日：2016-06-23
申请号：US14574093
申请日：2014-12-17
CPC分类号： G06T1/60 , G06T1/20 , G06T2200/28 , H04N13/139
摘要： Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., a local cache) are described. The pixel data may derive from an image capturing device (e.g., a color camera or a depth camera) in which individual pixel values are not a multiple of eight bits. In some embodiments, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one example, the DMA engine may be configured to identify and label one or more pixels as being within a particular range of pixel values and/or the DMA engine may be configured to label pixels as belonging to one or more pixel groups based on their pixel values.
摘要翻译： 描述了在将像素数据从第一存储器（例如，DRAM）到第二存储器（例如，本地高速缓存）的数据传输期间使用直接存储器访问（DMA）引擎预处理像素数据的方法。 像素数据可以从其中各个像素值不是8位的倍数的图像捕获设备（例如，彩色照相机或深度相机）导出。 在一些实施例中，DMA引擎可以在将像素数据写入第二存储器之前对像素数据执行各种图像处理操作。 在一个示例中，DMA引擎可以被配置为将一个或多个像素识别并标记为在像素值的特定范围内，和/或DMA引擎可以被配置为基于它们的像素组将像素标记为属于一个或多个像素组 像素值。
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公开(公告)号：US20160180494A1
公开(公告)日：2016-06-23
申请号：US14574100
申请日：2014-12-17
CPC分类号： G06T1/60 , G06T1/20 , G06T7/90 , G06T2207/10024 , G06T2207/10028
摘要： Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., an SRAM) are described. The pixel data may derive from a color camera or a depth camera in which individual pixel values are not a multiple of eight bits. In some cases, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one embodiment, the DMA engine may be configured to determine whether one or more pixels corresponding with the pixel data may be invalidated or skipped based on a minimum pixel value threshold and a maximum pixel value threshold and to embed pixel skipping information within unused bits of the pixel data.
摘要翻译： 描述了在从第一存储器（例如，DRAM）到第二存储器（例如，SRAM）的像素数据的数据传输期间使用直接存储器访问（DMA）引擎来预处理像素数据的方法。 像素数据可以从彩色相机或深度相机中得出，其中各个像素值不是8位的倍数。 在某些情况下，DMA引擎可以在将像素数据写入第二存储器之前对像素数据执行各种图像处理操作。 在一个实施例中，DMA引擎可以被配置为基于最小像素值阈值和最大像素值阈值来确定与像素数据相对应的一个或多个像素可能被无效或跳过，并且将像素跳过信息嵌入到未使用的位内 像素数据。
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4.发明授权Spacing periodic commands to a volatile memory for increased performance and decreased collision 失效将周期性命令间隔到易失性存储器，以提高性能和减少碰撞公开(公告)号：US08549217B2
公开(公告)日：2013-10-01
申请号：US12620065
申请日：2009-11-17
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G11C11/40611
摘要： A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis.
摘要翻译： 提供了周期性的命令间隔机制，用于将周期性命令（例如，刷新命令，ZQ校准等）分隔到易失性存储器（例如，SDRAM，DRAM，EDRAM等）中，以提高性能和减少碰撞。 在一个实施例中，监视周期性命令请求，并且如果在两个或更多请求之间检测到冲突，则冲突请求通过以芯片选择为基础施加的定时器偏移而相对于彼此间隔开。 周期性命令间隔机制可以与命令仲裁一起使用，以确保执行周期性命令而不会显着影响性能（例如，允许读取和写入流动）。 优选地，通过产生单独请求的初始序列来初始化周期性命令请求，初始序列中的每个连续请求通过以芯片选择为基础应用的定时器偏移相对于先前请求间隔开。
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5.发明授权Method and apparatus for preventing bus livelock due to excessive MMIO 有权用于防止由于过度的MMIO引起的总线活动锁定的方法和装置公开(公告)号：US08006013B2
公开(公告)日：2011-08-23
申请号：US12188115
申请日：2008-08-07
CPC分类号： G06F13/36
摘要： The disclosure relates to a method and apparatus to efficiently address livelock in a multi-processor system. In one embodiment, the disclosure is directed to a method for preventing a system bus livelock in a system having a plurality of processors communicating respectively through a plurality of bus masters to a plurality of IO Controllers across a system bus by: receiving at an MMIO state machine a plurality of snoop commands issued from the plurality of processors, identifying a first processor and a second processor from the plurality of processors, each of the first processor and the second processor having a first number of snoop commands in the input queue and a second number of responses in the output queue, the first number and the second number exceeding a threshold; issuing a burst prevention response to the first processor and the second process.
摘要翻译： 本公开涉及一种在多处理器系统中有效地解决活动锁定的方法和装置。 在一个实施例中，本公开涉及一种用于防止在具有通过多个总线主机通过系统总线分别通过多个总线主机通信到多个IO控制器的多个处理器的系统中的系统总线活动锁定的方法，即：以MMIO状态 从多个处理器发出多个窥探指令，从多个处理器识别第一处理器和第二处理器，第一处理器和第二处理器中的每一个在输入队列中具有第一数量的窥探命令，第二处理器 输出队列中的响应数量，第一个数字和第二个数字超过阈值; 对第一处理器和第二处理器发出突发预防响应。
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6.发明申请MOVING HARDWARE CONTEXT STRUCTURES IN MEMORY WHILE MAINTAINING SYSTEM OPERATION 有权在保持系统运行的情况下移动存储器中的硬件上下文结构公开(公告)号：US20080235478A1
公开(公告)日：2008-09-25
申请号：US12134052
申请日：2008-06-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0223
摘要： An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system.
摘要翻译： 适配器包括寄存器，本地上下文表和逻辑，其允许在计算机系统继续运行时将硬件上下文结构从存储器中的第一位置复制到存储器中的第二位置。 适配器中的本地上下文表从内存中的第一个位置加载了所需的上下文条目块。 寄存器中的值使适配器以不阻碍计算机系统操作的方式将上述条目的所需块写入存储器中的第二个位置。
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7.发明授权Moving hardware context structures in memory while maintaining system operation 有权在维护系统运行的同时，在内存中移动硬件上下文结构公开(公告)号：US07681003B2
公开(公告)日：2010-03-16
申请号：US12134052
申请日：2008-06-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0223
摘要： An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system.
摘要翻译： 适配器包括寄存器，本地上下文表和逻辑，其允许在计算机系统继续运行时将硬件上下文结构从存储器中的第一位置复制到存储器中的第二位置。 适配器中的本地上下文表从内存中的第一个位置加载了所需的上下文条目块。 寄存器中的值导致适配器以不阻止计算机系统操作的方式将上述条目的所需块写入存储器中的第二个位置。
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8.发明授权Concurrent read access and exclusive write access to data in shared memory architecture 有权共享内存架构中的数据并发读访问和独占写入访问公开(公告)号：US07308539B2
公开(公告)日：2007-12-11
申请号：US11016218
申请日：2004-12-17
CPC分类号： G06F12/0831 , G06F12/0835 , G06F12/0875
摘要： Concurrent read access and exclusive write access are provided in a shared memory architecture to permit one or more devices in the shared memory architecture to maintain read access to a block of memory such as a cache line while one device has exclusive permission to modify that block of memory. By doing so, a device that has permission to modify may make updates to its copy of the block of memory without invalidating other copies of the block of memory, and potentially enabling other devices to continue to read data from their respective copies of the block of memory without having to retrieve the updated copy of the block of memory.
摘要翻译： 在共享存储器架构中提供并发读取访问和独占写入访问，以允许共享存储器体系结构中的一个或多个设备保持对诸如高速缓存行之类的存储器块的读取访问，而一个设备具有修改该块 记忆。 通过这样做，具有修改权限的设备可以对存储器块的副本进行更新，而不使存储器块的其他副本无效，并且潜在地使其他设备能够继续从其相应副本的块读取数据 内存，而不必检索内存块的更新副本。
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公开(公告)号：US07941633B2
公开(公告)日：2011-05-10
申请号：US11958704
申请日：2007-12-18
CPC分类号： G06F12/0893 , G06F12/0864
摘要： A computer implemented method, apparatus and program product automatically optimizes hash function operation by recognizing when a first hash function results in an unacceptable number of cache misses, and by dynamically trying another hash function to determine which hash function results in the most cache hits. In this manner, hardware optimizes hash function operation in the face of changing loads and associated data flow patterns.
摘要翻译： 计算机实现的方法，装置和程序产品通过识别何时第一散列函数导致不可接受的数量的高速缓存未命中并且通过动态地尝试另一个散列函数来确定哪个哈希函数导致最多缓存命中，来自动优化哈希函数操作。 以这种方式，硬件在面对变化的负载和相关数据流模式时优化散列函数操作。
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10.发明申请Spacing Periodic Commands to a Volatile Memory for Increased Performance and Decreased Collision 失效将周期性命令间隔到易失性存储器，以提高性能和减少的冲突公开(公告)号：US20110119439A1
公开(公告)日：2011-05-19
申请号：US12620065
申请日：2009-11-17
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G11C11/40611
摘要： A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis.
摘要翻译： 提供了周期性的命令间隔机制，用于将周期性命令（例如，刷新命令，ZQ校准等）分隔到易失性存储器（例如，SDRAM，DRAM，EDRAM等）中，以提高性能和减少碰撞。 在一个实施例中，监视周期性命令请求，并且如果在两个或更多请求之间检测到冲突，则冲突请求通过以芯片选择为基础施加的定时器偏移而相对于彼此间隔开。 周期性命令间隔机制可以与命令仲裁一起使用，以确保执行周期性命令而不会显着影响性能（例如，允许读取和写入流动）。 优选地，通过产生单独请求的初始序列来初始化周期性命令请求，初始序列中的每个连续请求通过以芯片选择为基础应用的定时器偏移相对于先前请求间隔开。
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