公开(公告)号：US07609551B2

公开(公告)日：2009-10-27

申请号：US11860956

申请日：2007-09-25

申请人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： G11C14/00 ,  G11C16/04

CPC分类号： H01L29/792 ,  G11C11/404 ,  G11C11/4074 ,  G11C14/0018 ,  G11C2211/4016 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42344 ,  H01L29/785 ,  H01L29/78648

摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

摘要翻译： 本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态 通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态 通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

公开(公告)号：US07692963B2

公开(公告)日：2010-04-06

申请号：US11934337

申请日：2007-11-02

申请人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： G11C11/34

CPC分类号： G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.

摘要翻译： 本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流 的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。

公开(公告)号：US07977738B2

公开(公告)日：2011-07-12

申请号：US12497010

申请日：2009-07-02

申请人： Yoshihiro Minami ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

发明人： Yoshihiro Minami ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L27/1022 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

摘要翻译： 半导体存储器件包括电漂浮体; 来源 下水道 栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括具有与排水管相同的导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。

公开(公告)号：US20100019304A1

公开(公告)日：2010-01-28

申请号：US12497010

申请日：2009-07-02

申请人： Yoshihiro MINAMI ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

发明人： Yoshihiro MINAMI ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L27/1022 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

摘要翻译： 半导体存储器件包括电漂浮体; 来源 下水道 栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括与排水管相同导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。

公开(公告)号：US20070284661A1

公开(公告)日：2007-12-13

申请号：US11753704

申请日：2007-05-25

申请人： Takashi Yamada ,  Tomoaki Shino

发明人： Takashi Yamada ,  Tomoaki Shino

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/785

摘要： This disclosure concerns a semiconductor memory device comprising a semiconductor substrate; a first dielectric film provided on the semiconductor substrate; two Fins provided on the first dielectric film and made of a semiconductor material; a second dielectric film provided on facing inner side surfaces among side surfaces of the two Fins; a third dielectric film provided on outer side surfaces among side surfaces of the two Fins; a gate electrode provided via the second dielectric film between the inner side surfaces of the two Fins; and a plate electrode provided via the third dielectric film on the outer side surfaces of the two Fins, wherein the two Fins, the gate electrode, and the plate electrode are included in one memory cell.

摘要翻译： 本公开涉及包括半导体衬底的半导体存储器件; 设置在所述半导体基板上的第一电介质膜; 两个翅片设置在第一绝缘膜上并由半导体材料制成; 设置在所述两个金属丝的侧面的相对的内侧表面上的第二电介质膜; 设置在所述两个金属丝的侧面的外侧表面上的第三电介质膜; 在所述两个金属丝的内侧表面之间经由所述第二电介质膜设置的栅电极; 以及通过第三电介质膜设置在两个金属丝的外侧表面上的平板电极，其中两个金属丝，栅电极和平板电极都包含在一个存储单元中。

公开(公告)号：US20050110078A1

公开(公告)日：2005-05-26

申请号：US10767430

申请日：2004-01-30

申请人： Tomoaki Shino

发明人： Tomoaki Shino

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L29/7841 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7881

摘要： A semiconductor device includes a substrate, a semiconductor layer of a first conductivity type having a single-crystal structure, and a plurality of transistors each including a first gate electrode provided above the semiconductor layer with a first gate insulation film laid therebetween, a pair of impurity regions of a second conductivity type being provided in the semiconductor layer and each becoming a source or drain region, and a channel body of the first conductivity type provided in the semiconductor layer at a portion between these impurity regions. The device also includes a first gate line for common connection of the first gate electrodes of the transistors, a dielectric layer provided above the substrate in an extension direction of the first gate line, for supporting the semiconductor layer under the pair of impurity regions to thereby dielectrically isolate between the substrate and the semiconductor layer, a second gate electrode provided above the substrate in such a manner as to underlie the channel bodies of the transistors and oppose the channel bodies with a second gate insulation film laid therebetween, the second gate electrode having a gate length larger than a onefold value of a gate length of the first gate electrode and yet less than or equal to thrice the gate length, and a second gate line provided above the substrate along the extension direction of the first gate line while being placed between portions of the dielectric layer underlying the pair of impurity regions, the second gate line being for common connection of the second gate electrode.

摘要翻译： 半导体器件包括衬底，具有单晶结构的第一导电类型的半导体层和多个晶体管，每个晶体管包括设置在半导体层上方的第一栅电极，第一栅极绝缘膜位于其间，一对 第二导电类型的杂质区域设置在半导体层中并且各自成为源极或漏极区域，以及在这些杂质区域之间的部分处设置在半导体层中的第一导电类型的沟道体。 该器件还包括用于共同连接晶体管的第一栅电极的第一栅极线，在第一栅极线的延伸方向上设置在衬底上方的电介质层，用于将半导体层支撑在该对杂质区下面 在衬底和半导体层之间介电隔离;第二栅电极，其设置在衬底上方，以便在晶体管的沟道本体的下面，并与第二栅绝缘膜相对的通道体相对，第二栅电极具有 栅极长度大于第一栅电极的栅极长度的一倍值，但小于或等于栅极长度的三倍;以及第二栅极线，沿着第一栅极线的延伸方向设置在衬底上方，同时放置 在一对杂质区下面的介电层的部分之间，第二栅极线用于公共连接 第二栅电极的作用。

公开(公告)号：US07795658B2

公开(公告)日：2010-09-14

申请号：US11677329

申请日：2007-02-21

申请人： Tomoaki Shino

发明人： Tomoaki Shino

IPC分类号： H01L29/94

CPC分类号： H01L27/1203 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10897 ,  H01L27/1207 ,  H01L29/7841

摘要： A semiconductor memory device includes a supporting substrate including semiconductor materials. The memory device also includes an insulation film provided above the supporting substrate. The memory device further includes a first diffusion layer provided on the insulation film. In addition, the memory device includes a second diffusion layer provided on the insulation film. The memory device additionally includes a body region provided between the first diffusion layer and the second diffusion layer. The body region is in an electrically floating state and accumulates or releases electric charges for storing data. Also, the memory device includes a semiconductor layer penetrating the insulation film and electrically connecting the second diffusion layer to the supporting substrate to release electric charges from the second diffusion layer. Further, the memory device includes a gate insulation film provided on the body region. Additionally, the memory device includes a gate electrode provided on the gate insulation film.

摘要翻译： 半导体存储器件包括包括半导体材料的支撑衬底。 存储装置还包括设置在支撑基板上方的绝缘膜。 存储器件还包括设置在绝缘膜上的第一扩散层。 此外，存储器件包括设置在绝缘膜上的第二扩散层。 存储装置还包括设置在第一扩散层和第二扩散层之间的主体区域。 身体区域处于电浮动状态，并且累积或释放用于存储数据的电荷。 此外，存储器件包括穿透绝缘膜并将第二扩散层电连接到支撑衬底以从第二扩散层释放电荷的半导体层。 此外，存储器件包括设置在身体区域上的栅极绝缘膜。 此外，存储器件包括设置在栅极绝缘膜上的栅电极。

公开(公告)号：US07256459B2

公开(公告)日：2007-08-14

申请号：US11044348

申请日：2005-01-28

申请人： Tomoaki Shino

发明人： Tomoaki Shino

IPC分类号： H01L27/01 ,  H01L27/084 ,  H01L27/097 ,  H01L27/075

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10873 ,  H01L29/7841

摘要： A semiconductor memory device includes transistors, each including a first-conductivity-type semiconductor layer formed on a semiconductor substrate via a first insulating film, a second-conductivity-type source/drain regions formed in the semiconductor layer, a first-conductivity-type body region formed between the source region and the drain region in the semiconductor layer, the body region being electrically floating, and a gate electrode formed on a surface of a central portion of the body region via a second insulating film. In a section along a word line, which connects the gate electrodes together, a length of a boundary between the central portion of the body region and the second insulating film is smaller than a length of a boundary between the body region and the first insulating film. A second-conductivity-type counter impurity is doped in a surface portion of the central portion of the body region on which the second insulating film is formed.

摘要翻译： 半导体存储器件包括晶体管，每个晶体管包括经由第一绝缘膜形成在半导体衬底上的第一导电型半导体层，形成在半导体层中的第二导电型源/漏区，第一导电型 在半导体层中的源极区域和漏极区域之间形成的主体区域，主体区域电浮置，以及通过第二绝缘膜形成在体区域的中心部分的表面上的栅极电极。 在将栅电极连接在一起的字线的部分中，体区的中央部与第二绝缘膜之间的边界的长度小于体区与第一绝缘膜之间的边界的长度 。 在形成第二绝缘膜的体区的中心部分的表面部分中掺杂有第二导电型的计数杂质。

公开(公告)号：US20060049444A1

公开(公告)日：2006-03-09

申请号：US11044348

申请日：2005-01-28

申请人： Tomoaki Shino

发明人： Tomoaki Shino

IPC分类号： H01L29/94

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10873 ,  H01L29/7841

摘要： According to the present invention, there is provided a semiconductor device comprising: a plurality of transistors each having a semiconductor substrate, a first-conductivity-type semiconductor layer formed on said semiconductor substrate via a first insulating film, and having a single-crystal structure, a second-conductivity-type source region and second-conductivity-type drain region formed in said semiconductor layer, a first-conductivity-type body region formed between said source region and said drain region in said semiconductor layer, and electrically floating, and a gate electrode formed on a central portion of a surface of said body region via a second insulating film; an element isolation insulating film which isolates said body regions in adjacent transistors of said plurality of transistors; a word line which connects said gate electrodes of said plurality of transistors together; a bit line electrically connected to said drain region; and a source line electrically connected to said source region, wherein in a section along said word line, an area in which said body region contacts said second insulating film is smaller than an area in which said body region contacts said first insulating film.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：多个晶体管，每个具有半导体衬底，经由第一绝缘膜形成在所述半导体衬底上的第一导电型半导体层，并具有单晶结构 形成在所述半导体层中的第二导电型源极区域和第二导电型漏极区域，形成在所述半导体层的所述源极区域和所述漏极区域之间的电气浮动的第一导电型体区域，以及 栅电极，经由第二绝缘膜形成在所述体区的表面的中心部分上; 元件隔离绝缘膜，其隔离所述多个晶体管的相邻晶体管中的所述体区; 将所述多个晶体管的所述栅电极连接在一起的字线; 电连接到所述漏区的位线; 以及与所述源极区域电连接的源极线，其中在所述字线的截面中，所述体区域与所述第二绝缘膜接触的区域小于所述体区域与所述第一绝缘膜接触的区域。

公开(公告)号：US06174779B1

公开(公告)日：2001-01-16

申请号：US09267775

申请日：1999-03-15

申请人： Tomoaki Shino ,  Takashi Yamada ,  Makoto Yoshimi ,  Shigeru Kawanaka ,  Hideaki Nii ,  Kazumi Inoh ,  Tsuneaki Fuse ,  Sadayuki Yoshitomi ,  Mamoru Terauchi

发明人： Tomoaki Shino ,  Takashi Yamada ,  Makoto Yoshimi ,  Shigeru Kawanaka ,  Hideaki Nii ,  Kazumi Inoh ,  Tsuneaki Fuse ,  Sadayuki Yoshitomi ,  Mamoru Terauchi

IPC分类号： H01L218228

CPC分类号： H01L29/66265 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7317

摘要： In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.

摘要翻译： 在横向双极晶体管中，通过使用部分重叠的两个掩模图案，其发射极区域，基极区域，链路基极区域等与掩模的侧壁自对准。 因此，不依赖于掩模对准精度，这些区域被精确控制位置关系。 因此，如此获得的横向双极晶体管的基极的寄生电阻和发射极与基极之间的寄生结电容减小，并且由于链路基极区域的长度的波动引起的特性的变化减轻， 发射极 - 基极结和发射极和集电极的相对位置，并且可以以高再现性制造。