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    SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREFOR
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREFOR 审中-公开
    半导体存储器件及其驱动方法

    公开(公告)号：US20110188288A1

    公开(公告)日：2011-08-04

    申请号：US12822952

    申请日：2010-06-24

    申请人： Yoshihiro MINAMI

    发明人： Yoshihiro MINAMI

    IPC分类号： G11C11/22 ,  H01L27/115

    CPC分类号： G11C11/22 ,  G11C11/223 ,  H01L27/1159 ,  H01L27/11597

    摘要： A memory includes a first conductive-type first diffusion layer on the semiconductor substrate; second conductive-type bodies on the first diffusion layer(s); first conductive-type second diffusion layers on the bodies; first gate dielectric films comprising ferroelectric films and provided on first side surfaces of the bodies; second gate dielectric films comprising ferroelectric films and provided on second side surfaces of the bodies; first gate electrodes on the first gate dielectric film; and second gate electrodes on the second gate dielectric film, wherein the first and the second diffusion layers, the body, the first and the second gate dielectric films, and the first and the second gate electrodes constitute memory cells, and each of the memory cells stores a plural pieces of logical data depending on a polarization state of the first gate dielectric film and on a polarization state of the second gate dielectric film.

    摘要翻译： 存储器包括半导体衬底上的第一导电型第一扩散层; 第一导电型体在第一扩散层上; 主体上的第一导电型第二扩散层; 包括铁电体膜的第一栅极电介质膜并且设置在所述主体的第一侧表面上; 包括铁电体膜并设置在所述主体的第二侧表面上的第二栅极介电膜; 第一栅极电极在第一栅极电介质膜上; 和第二栅极电极，其中第一和第二扩散层，主体，第一和第二栅极电介质膜以及第一和第二栅电极构成存储单元，并且每个存储单元 根据第一栅极电介质膜的极化状态和第二栅极电介质膜的极化状态存储多条逻辑数据。

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20110182102A1

    公开(公告)日：2011-07-28

    申请号：US12730089

    申请日：2010-03-23

    申请人： Yoshihiro MINAMI

    发明人： Yoshihiro MINAMI

    IPC分类号： G11C11/22 ,  G11C7/00

    CPC分类号： H01L21/84 ,  G11C11/22 ,  G11C11/223 ,  G11C11/5657 ,  G11C2211/562 ,  G11C2211/5648 ,  H01L27/10802 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

    摘要： A memory includes memory cells on a semiconductor layer, in which each of the memory cells includes a source layer and a drain layer in the semiconductor layer; an electrically floating body region provided in the semiconductor layer between the source layer and the drain layer and configured to accumulate or discharge electric charges in order to store logical data; a gate dielectric film provided on the body region and comprising a ferroelectric film with polarization characteristics; and a gate electrode provided on the gate dielectric film above the body region, wherein each memory cell stores a plurality of logical data depending on an amount of electric charges accumulated in the body region and on a polarization state of the ferroelectric film.

    摘要翻译： 存储器包括半导体层上的存储单元，其中每个存储单元包括半导体层中的源极层和漏极层; 电浮置体区域，设置在所述源极层和漏极层之间的所述半导体层中，并且被配置为积累或放电电荷以便存储逻辑数据; 设置在所述本体区域上并具有极化特性的铁电体膜的栅极电介质膜; 以及设置在所述体区域上方的所述栅极电介质膜上的栅电极，其中，每个存储单元根据所述体区中累积的电荷量和所述强电介质膜的极化状态来存储多个逻辑数据。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07154151B2

    公开(公告)日：2006-12-26

    申请号：US11015036

    申请日：2004-12-20

    申请人： Yoshihiro Minami

    发明人： Yoshihiro Minami

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0255 ,  H01L27/1203 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device comprises a semiconductor substrate; an embedded insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the embedded insulating layer; a transistor including a first conductivity type source layer formed within the semiconductor layer, a first conductivity type drain layer formed in the semiconductor layer, and a channel forming region between the source layer and the drain layer; and an embedded insulating layer protective diode including a second conductivity type first diffusion layer and a first conductivity type second diffusion layer, the first diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region, the second diffusion layer being provided adjacently to the first diffusion layer and electrically connected to at least one of the source layer, the drain layer and the channel forming region.

    摘要翻译： 半导体器件包括半导体衬底; 设置在半导体基板上的嵌入式绝缘层; 设置在所述嵌入绝缘层上的半导体层; 包括形成在所述半导体层内的第一导电类型源极层，形成在所述半导体层中的第一导电类型漏极层和所述源极层与所述漏极层之间的沟道形成区域的晶体管; 以及包括第二导电型第一扩散层和第一导电型第二扩散层的嵌入式绝缘层保护二极管，所述第一扩散层与所述沟道形成区域正下方的半导体衬底区域处于相同的电位，所述第二扩散层为 与第一扩散层相邻并且电连接到源极层，漏极层和沟道形成区域中的至少一个。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07995369B2

    公开(公告)日：2011-08-09

    申请号：US12332595

    申请日：2008-12-11

    申请人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

    发明人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

    IPC分类号： G11C17/00

    CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/1203

    摘要： This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.

    摘要翻译： 本公开涉及包括位线的半导体存储器件; 字线 布置成对应于位线和字线的交叉点的半导体层; 连接在第一表面区域和位线之间的位线触点，第一表面区域是半导体层指向字线和位线的表面区域的一部分; 以及形成在与所述第一表面区域相邻的第二表面区域上的字线绝缘膜，所述第二表面区域是所述表面区域之外的一部分，所述字线绝缘膜使所述半导体层和所述字线电绝缘， 其中半导体层，字线和字线绝缘膜形成电容器，并且当在字线和位线之间给出电位差时，字线绝缘膜被破坏以便存储数据。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20070215916A1

    公开(公告)日：2007-09-20

    申请号：US11609013

    申请日：2006-12-11

    申请人： Yoshihiro MINAMI ,  Tomoaki SHINO

    发明人： Yoshihiro MINAMI ,  Tomoaki SHINO

    IPC分类号： H01L21/8234 ,  H01L29/76

    CPC分类号： H01L29/7841 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10894

    摘要： This disclosure concerns a method of manufacturing a semiconductor device including preparing a support substrate including a surface region consisting of a semiconductor single crystal; forming a porous semiconductor layer by transforming the surface region of the support substrate into a porous layer; epitaxially growing a single-crystal semiconductor layer on the porous semiconductor layer; forming an opening reaching the porous semiconductor layer by removing a part of the single-crystal semiconductor layer; forming a cavity between the single-crystal semiconductor layer and the support substrate by removing the porous semiconductor layer through the opening; and filling the cavity with an insulating film or a conductive film.

    摘要翻译： 本公开涉及一种制造半导体器件的方法，包括制备包括由半导体单晶构成的表面区域的支撑衬底; 通过将所述支撑基板的表面区域变换为多孔层来形成多孔半导体层; 在多孔半导体层上外延生长单晶半导体层; 通过去除一部分单晶半导体层形成到达多孔半导体层的开口; 通过所述开口去除所述多孔半导体层，在所述单晶半导体层和所述支撑基板之间形成空腔; 并用绝缘膜或导电膜填充空腔。

    High withstand voltage semiconductor device
    9.
    发明授权
    High withstand voltage semiconductor device 失效
    高耐压半导体器件

    公开(公告)号：US5969400A

    公开(公告)日：1999-10-19

    申请号：US614340

    申请日：1996-03-12

    申请人： Takashi Shinohe ,  Yoshihiro Minami ,  Ichiro Omura

    发明人： Takashi Shinohe ,  Yoshihiro Minami ,  Ichiro Omura

    IPC分类号： H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/739 ,  H01L29/861 ,  H01L23/58

    CPC分类号： H01L27/0761 ,  H01L29/0615 ,  H01L29/0834 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/8611 ,  H01L2924/0002

    摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type having first and second main surfaces, a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer, the second semiconductor layer including a first region having a relatively high injection efficiency and a second region having a relatively low injection efficiency and the first region being surrounded by the second region, a third semiconductor layer of the first conductivity type formed on the second main surface of the first semiconductor layer, a first electrode selectively formed on the second semiconductor layer of the second conductivity type and connected to at least the first region, and a second electrode formed on the third semiconductor layer of the first conductivity type.

    摘要翻译： 半导体器件包括具有第一和第二主表面的第一导电类型的第一半导体层，选择性地形成在第一半导体层的第一主表面上的第二导电类型的第二半导体层，第二半导体层包括第一区域 具有相对较高的注入效率和具有相对低的注入效率的第二区域，并且第一区域被第二区域包围，形成在第一半导体层的第二主表面上的第一导电类型的第三半导体层，第一 电极选择性地形成在第二导电类型的第二半导体层上并连接到至少第一区域，第二电极形成在第一导电类型的第三半导体层上。

    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20100019304A1

    公开(公告)日：2010-01-28

    申请号：US12497010

    申请日：2009-07-02

    申请人： Yoshihiro MINAMI ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

    发明人： Yoshihiro MINAMI ,  Takashi Ohsawa ,  Tomoaki Shino ,  Takeshi Hamamoto ,  Akihiro Nitayama

    IPC分类号： H01L27/06 ,  H01L21/8249

    CPC分类号： H01L27/1022 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

    摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

    摘要翻译： 半导体存储器件包括电漂浮体; 来源 下水道 栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括与排水管相同导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。