Processor and program execution method capable of efficient program execution
    4.
    发明授权
    Processor and program execution method capable of efficient program execution 有权
    处理器和程序执行方法能够高效地执行程序

    公开(公告)号:US08719827B2

    公开(公告)日:2014-05-06

    申请号:US13179614

    申请日:2011-07-11

    IPC分类号: G06F9/46 G06F9/00 G06F1/00

    摘要: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

    摘要翻译: 一种处理器,用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元,其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组,并且每当经过第一预定时间时切换所述选择目标; 恢复单元,其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元,其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元,其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

    Processor and program execution method capable of efficient program execution
    5.
    发明授权
    Processor and program execution method capable of efficient program execution 有权
    处理器和程序执行方法能够高效地执行程序

    公开(公告)号:US07386707B2

    公开(公告)日:2008-06-10

    申请号:US10338408

    申请日:2003-01-08

    IPC分类号: G06F9/30 G06F9/40

    摘要: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

    摘要翻译: 一种处理器,用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元,其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组,并且每当经过第一预定时间时切换所述选择目标; 恢复单元,其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元,其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元,其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

    Circuit group control system
    9.
    发明授权
    Circuit group control system 有权
    电路组控制系统

    公开(公告)号:US06901454B2

    公开(公告)日:2005-05-31

    申请号:US10289993

    申请日:2002-11-07

    CPC分类号: G06F9/4843

    摘要: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

    摘要翻译: 一种电路组控制系统,其从主处理器接收第一命令序列和第二命令序列,每个命令序列由多个命令组成,每个命令由多个电路中的一个执行,并且使任何可用的电路 按照每个命令序列中的排列顺序逐个执行命令。 电路组控制系统通过使电路(第二电路)在第二命令序列中执行命令而实现多个命令序列的并发执行,而另一电路(第一电路)在第一命令序列中执行另一命令。

    PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION
    10.
    发明申请
    PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION 有权
    能够有效执行计划的执行者和计划执行方法

    公开(公告)号:US20080215858A1

    公开(公告)日:2008-09-04

    申请号:US12110539

    申请日:2008-04-28

    IPC分类号: G06F9/30

    摘要: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

    摘要翻译: 一种处理器,用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元,其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组,并且每当经过第一预定时间时切换所述选择目标; 恢复单元,其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元,其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元,其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。