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公开(公告)号：US20050248556A1
公开(公告)日：2005-11-10
申请号：US11018873
申请日：2004-12-21
IPC分类号： G02F1/13 , G02F1/133 , G02F1/1345 , G02F1/136 , G02F1/1362 , G02F1/1368 , G03B21/00 , G09G3/20 , G09G3/36 , G09G5/00
CPC分类号： G02F1/136286 , G02F2001/133391 , G09G3/3666 , G09G2310/0205 , G09G2310/0275 , G09G2310/0283 , G09G2310/0297 , G09G2320/0233 , G09G2320/0252
摘要： A display device having extremely short writing time to a pixel such as the liquid crystal display device of a dot sequential drive method using a single-crystal silicon transistor as a switching element is provided in which in the case where a display area is divided into two or more areas, the degradation of picture quality is prevented to perform a high definition display. In a display device of a matrix drive method in which gate lines X in the row direction and data lines Y in the column direction are arranged in matrix shape and a pixel P is arranged at the intersection of the gate line and the data line, a display area is divided into two or more areas 1A and 1B which are driven independently from each other; wiring layout of signal lines 8A and 8B which transfer display data d to each of the areas 1A and 1B is approximately symmetrical with a division boundary line of those areas positioned in between; and control unit 12 which makes a control to perform writing of the display data at least to the pixels P next to each other with the division boundary line positioned in between at approximately the same timing.
摘要翻译： 提供了一种具有非常短的写入时间的显示装置，其中诸如使用单晶硅晶体管作为开关元件的点顺序驱动方法的液晶显示装置的像素，其中在将显示区域分成两部分的情况下 或更多的区域，防止图像质量的劣化来执行高清晰度显示。 在行方向上的栅极线X和列方向上的数据线Y以矩阵形状排列并且像素P布置在栅极线和数据线的交叉处的矩阵驱动方法的显示装置中， 显示区域被分成彼此独立地驱动的两个或更多个区域1A和1B; 将显示数据d传送到区域1A和1B中的每一个的信号线8A和8B的接线布局与位于其间的那些区域的划分边界线大致对称; 以及控制单元12，其进行控制，以使分割边界线位于大致相同的定时之间，至少对彼此相邻的像素P执行写入。
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公开(公告)号：US08547316B2
公开(公告)日：2013-10-01
申请号：US12197392
申请日：2008-08-25
申请人： Yusuke Doi , Tomoro Yoshinaga , Naoki Ando , Seisan Hoshimoto , Kouji Tada , Tomoaki Kichimi , Koichi Katagawa
发明人： Yusuke Doi , Tomoro Yoshinaga , Naoki Ando , Seisan Hoshimoto , Kouji Tada , Tomoaki Kichimi , Koichi Katagawa
CPC分类号： G09G3/3688 , G09G3/3655 , G09G2300/0408 , G09G2310/0297 , G09G2320/0673 , G09G2340/0435
摘要： A display apparatus includes a display panel, a panel substrate including a data line driver, a controller connected to the panel substrate, and a connection unit provided in the panel substrate. The controller selects M signal lines from N signal lines (M is a natural number satisfying M≦N) in accordance with a frame rate of a video data, and transmits M-phase video data to the panel substrate via the selected M signal lines. The data line driver controls the switching circuits of the connection unit in accordance with the frame rate of the video data to connect the M signal lines via which the video data is transmitted, to the data lines, and sequentially selects the M data lines to supply each piece of the video data transmitted via the M signal lines to each pixel connected to the selected M data lines.
摘要翻译： 显示装置包括显示面板，包括数据线驱动器的面板基板，连接到面板基板的控制器和设置在面板基板中的连接单元。 控制器根据视频数据的帧速率从N条信号线（M为满足M @ N的自然数）中选择M条信号线，并通过选定的M条信号线将M相视频数据发送到面板基板。 数据线驱动器根据视频数据的帧速率控制连接单元的切换电路，以将通过其发送视频数据的M条信号线连接到数据线，并且依次选择M条数据线以供应 每条视频数据通过M条信号线发送到连接到所选M条数据线的每个像素。
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公开(公告)号：US20090058763A1
公开(公告)日：2009-03-05
申请号：US12197392
申请日：2008-08-25
申请人： Yusuke Doi , Tomoro Yoshinaga , Naoki Ando , Seisan Hoshimoto , Kouji Tada , Tomoaki Kichimi , Koichi Katagawa
发明人： Yusuke Doi , Tomoro Yoshinaga , Naoki Ando , Seisan Hoshimoto , Kouji Tada , Tomoaki Kichimi , Koichi Katagawa
IPC分类号： G09G3/20
CPC分类号： G09G3/3688 , G09G3/3655 , G09G2300/0408 , G09G2310/0297 , G09G2320/0673 , G09G2340/0435
摘要： A display apparatus includes a display panel, a panel substrate including a data line driver, a controller connected to the panel substrate, and a connection unit provided in the panel substrate. The controller selects M signal lines from N signal lines (M is a natural number satisfying M≦N) in accordance with a frame rate of a video data, and transmits M-phase video data to the panel substrate via the selected M signal lines. The data line driver controls the switching circuits of the connection unit in accordance with the frame rate of the video data to connect the M signal lines via which the video data is transmitted, to the data lines, and sequentially selects the M data lines to supply each piece of the video data transmitted via the M signal lines to each pixel connected to the selected M data lines.
摘要翻译： 显示装置包括显示面板，包括数据线驱动器的面板基板，连接到面板基板的控制器和设置在面板基板中的连接单元。 控制器根据视频数据的帧速率从N条信号线（M为满足M <= N的自然数）中选择M条信号线，并通过选定的M条信号线将M相视频数据发送到面板基板 。 数据线驱动器根据视频数据的帧速率控制连接单元的切换电路，以将通过其发送视频数据的M条信号线连接到数据线，并且依次选择M条数据线以供应 每条视频数据通过M条信号线发送到连接到所选M条数据线的每个像素。
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公开(公告)号：US09483972B2
公开(公告)日：2016-11-01
申请号：US13606995
申请日：2012-09-07
申请人： Tomoro Yoshinaga
发明人： Tomoro Yoshinaga
CPC分类号： G09G3/2033 , G09G2310/08 , G09G2320/0266 , G09G2320/0271
摘要： A display method includes: performing display by driving a display pixel at a drive interval that conforms to a weight of each bit in a gray-scale code that includes the bits; and so correcting the drive interval, the gray-scale code, or both of the drive interval and the gray-scale code as to change a luminance of the display pixel smoothly.
摘要翻译： 显示方法包括：通过以包括比特的灰度代码中的每个比特的权重的驱动间隔驱动显示像素来执行显示; 并且因此校正驱动间隔，灰度代码或驱动间隔和灰度代码两者以平滑地改变显示像素的亮度。
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公开(公告)号：US20130050305A1
公开(公告)日：2013-02-28
申请号：US13567671
申请日：2012-08-06
申请人： Tomoro Yoshinaga
发明人： Tomoro Yoshinaga
IPC分类号： G09G5/10
CPC分类号： G09G3/2022 , G09G2300/0857
摘要： A drive circuit includes: a division section and an ON-OFF-period control section. The division section divides one frame period into a plurality of subfields, and divides each of one or more of the plurality of subfields to generate a plurality of division subfields. Each of the subfields corresponds to each bit of gray-scale data and has a period corresponding to a weight of the corresponding bit, and each of the one or more of the subfields has the period that is relatively long and is divided into periods each equal to the period of the subfield that is relatively short. The ON-OFF-period control section controls a ratio of an ON period or an OFF period to the one frame period, by turning on or off an electro-optical device of each pixel according to the bit corresponding to each of the subfields and each of the division subfields.
摘要翻译： 驱动电路包括：分割部和开关周期控制部。 分割部将一帧周期分割为多个子场，并且分割多个子场中的一个或多个子场中的每一个以生成多个分割子场。 每个子场对应于灰度数据的每个位，并且具有对应于相应位的权重的周期，并且一个或多个子场中的每一个具有相对较长的周期，并且被划分为每个相等的周期 到子域相对较短的时期。 开关周期控制部通过根据与各个子场对应的位对应的每个像素的电光装置来接通或关闭，从而控制ON周期或OFF周期与一帧周期的比率 的分区子字段。
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公开(公告)号：US08963967B2
公开(公告)日：2015-02-24
申请号：US13567669
申请日：2012-08-06
申请人： Tomoro Yoshinaga
发明人： Tomoro Yoshinaga
CPC分类号： G09G3/36 , G09G3/2033 , G09G2310/027 , G09G2320/0209 , G09G2320/0266
摘要： A drive circuit includes: a division section that divides one frame period into a subfields, and divides each of one or more of the subfields to generate division subfields; a correction section that corrects, when bit arrays of the gray-scale data corresponding to respective two pixels next to each other are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two pixels to bring this bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two pixels, while maintaining gray-scale; and an ON-OFF-period control section that controls a ratio of an ON period or an OFF period to the one frame period, by turning on or off a liquid crystal cell of each of pixels according to the bit corresponding to each of the subfields and each of the division subfields.
摘要翻译： 驱动电路包括：划分部分，将一个帧周期分成子场，并且划分一个或多个子场中的每一个以产生除法子场; 校正部，当对应于彼此相邻的两个像素的灰度数据的位阵列彼此不同时，校正灰度数据的位阵列对应于两个像素的第一像素，以带来 该比特阵列更靠近对应于两个像素的第二像素的灰度数据的比特阵列，同时保持灰度级; 以及开关周期控制部，其通过根据与每个子场对应的位来接通或关闭每个像素的液晶单元来控制ON周期或OFF周期与一帧周期的比率 和每个划分子字段。
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公开(公告)号：US08502810B2
公开(公告)日：2013-08-06
申请号：US12771619
申请日：2010-04-30
申请人： Tomoro Yoshinaga , Takashi Hirakawa
发明人： Tomoro Yoshinaga , Takashi Hirakawa
CPC分类号： G09G3/3677 , G09G3/001 , G09G3/003 , G09G2310/0205 , G09G2310/021 , G09G2310/0235 , G09G2320/0242 , G09G2320/0261 , G09G2340/0435 , H04N13/341 , H04N13/398
摘要： A display device includes: a pixel array unit including a plurality of scanning lines and a plurality of signal lines; a scanning line driving unit that sequentially applies a driving voltage to the plurality of scanning lines according to a shift timing indicated by a shift clock; a signal line driving unit that drives the plurality of signal lines on the basis of an input video signal, and a clock adjusting unit that adjusts the shift clock such that there are n (n is a natural number equal to or greater than 2) shift timings within each one horizontal line period for which an image signal corresponding to one horizontal line is displayed.
摘要翻译： 显示装置包括：像素阵列单元，包括多条扫描线和多条信号线; 扫描线驱动单元，根据由移位时钟指示的移位定时，顺序对多条扫描线施加驱动电压; 基于输入视频信号驱动多条信号线的信号线驱动单元，以及调整移位时钟以使n（n为2以上的自然数）移位的时钟调整单元 显示与一条水平线相对应的图像信号的每个水平线周期内的定时。
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8.发明申请公开(公告)号：US20130076802A1
公开(公告)日：2013-03-28
申请号：US13612060
申请日：2012-09-12
申请人： Tomoro Yoshinaga
发明人： Tomoro Yoshinaga
IPC分类号： G09G5/10
CPC分类号： G09G3/2022 , G09G2310/0205 , G09G2310/0216 , G09G2310/0218 , G09G2310/0227 , G09G2310/08
摘要： A drive circuit includes: a control section generating address information by which a horizontal line to be driven in a display section is designated, the display section including a plurality of display pixels; and a driving section driving, at a drive interval that conforms to a weight of each bit in a gray-scale code that includes the bits, the display pixels based on a value of each of the bits, within a unit driving period that is set to drive the horizontal line designated by the address information. The control section sets a start timing of the unit driving period on an optional basis.
摘要翻译： 驱动电路包括：控制部分，其生成地址信息，通过该地址信息指定要在显示部分中驱动的水平线，所述显示部分包括多个显示像素; 以及驱动部，在设定的单位驱动期间内，以与包含所述位的灰度代码中的每个比特的权重相对应的驱动间隔，基于每个比特的值驱动所述显示像素 驱动由地址信息指定的水平线。 控制部根据任意的基准设定单位驱动期间的开始时刻。
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公开(公告)号：US20130050299A1
公开(公告)日：2013-02-28
申请号：US13567666
申请日：2012-08-06
申请人： Tomoro Yoshinaga
发明人： Tomoro Yoshinaga
IPC分类号： G09G5/10
CPC分类号： G09G3/2022 , G09G2310/027
摘要： There is provided a driving circuit driving pixels each including an electro-optical device and a memory, in a display. The driving circuit includes: a dividing section dividing one frame period into subblocks composed of subfields, the subfields corresponding to respective bits of gray-scale data and having period lengths commensurate with weights of the corresponding bits; and an ON-OFF period control section controlling a ratio of an ON period or an OFF period to one frame period by bringing an electro-optical device of the pixel into an on state or an off state according to a corresponding bit in each of the subfields. On a subblock by subblock basis, the ON-OFF period control section selects scan lines whose number is less by one than a number of the subfields included in a relevant subblock, and again selects one of the selected scan lines during a same subblock period.
摘要翻译： 在显示器中提供驱动电路驱动像素，每个像素包括电光器件和存储器。 驱动电路包括：将一个帧周期划分成由子场组成的子块的分割部分，对应于灰度数据的各个比特并且具有与相应比特的权重相称的周期长度的子场; 以及ON-OFF周期控制部，其通过使像素的电光装置根据每个所述像素的对应位而处于接通状态或截止状态来控制ON周期或OFF周期与一个帧周期的比率 子场 在基于子块的子块的基础上，ON-OFF周期控制部选择数量比包含在相关子块中的子数少1倍的扫描线，并且在相同子块周期期间再次选择所选择的扫描线之一。
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公开(公告)号：US20130050286A1
公开(公告)日：2013-02-28
申请号：US13567675
申请日：2012-08-06
申请人： Tomoro Yoshinaga , Taro Ichitsubo
发明人： Tomoro Yoshinaga , Taro Ichitsubo
CPC分类号： G09G3/3648 , G09G3/2022 , G09G3/36 , G09G3/38 , G09G2320/0209 , G09G2320/0266 , G09G2320/0271 , H04N7/173
摘要： There is provided a driving circuit driving pixels in a display, the pixels each including a liquid crystal cell and a memory. The driving circuit includes: a dividing section dividing one frame period into subfields, the subfields corresponding to respective bits of gray-scale data and having period lengths commensurate with weights of the corresponding bits; a correction section correcting, when bit sequences of two sets of gray-scale data corresponding to two pixels adjacent to each other differ from each other, gray-scale data having a higher gray-scale level out of the two set of gray-scale data, to further increase the gray-scale level thereof; and an ON-OFF period control section controlling a ratio of an ON period or an OFF period to one frame period by bringing the liquid crystal cell of the pixel into an on state or an off state according to a corresponding bit in each of the subfields.
摘要翻译： 提供了驱动显示器中的像素的驱动电路，每个像素包括液晶单元和存储器。 驱动电路包括：将一个帧周期分成子场的分割部分，对应于灰度数据的各个比特并且具有与相应比特的权重相称的周期长度的子场; 校正部，当对应于彼此相邻的两个像素的两组灰度数据的位序列彼此不同时，校正灰度级数据，灰度级数据在两组灰度数据中具有较高的灰度级 进一步提高其灰度级; 以及ON-OFF周期控制部，其通过使像素的液晶单元根据每个子场中的相应位进入导通状态或截止状态来控制ON周期或OFF周期与一个帧周期的比率 。
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