公开(公告)号：US06642605B2

公开(公告)日：2003-11-04

申请号：US10162244

申请日：2002-06-04

申请人： Tomotaka Fujisawa ,  Chihiro Arai

发明人： Tomotaka Fujisawa ,  Chihiro Arai

IPC分类号： H01L2900

CPC分类号： H01L27/075 ,  H01L27/0761

摘要： In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.

摘要翻译： 在具有使用双极型晶体管的结型二极管的半导体器件及其制造方法中，提高了二极管电流与漏电流的比例，并且在不增加处理的情况下提高了闭锁电阻。 形成p型半导体衬底，集电极掩埋区和n型外延层，在n型外延层中形成ap型第一杂质区，在第一杂质区形成n型第二杂质区， +>沉降片，并且形成集电极，在第一和第二杂质区上形成有公共电极。

公开(公告)号：US06380602B1

公开(公告)日：2002-04-30

申请号：US09557689

申请日：2000-04-25

申请人： Tomotaka Fujisawa ,  Chihiro Arai

发明人： Tomotaka Fujisawa ,  Chihiro Arai

IPC分类号： H01L3106

CPC分类号： H01L27/1443

摘要： A semiconductor device in which a photoreceptor element and a semiconductor element are formed on a common semiconductor substrate, includes: a substrate of a first conductive type; and a semiconductor layer of a second conductive type formed on the substrate; wherein the photoreceptor element is composed of the substrate and the semiconductor layer; and an impurity concentration region of the first conductive type having an impurity concentration higher than that of the substrate is provided at a position under the semiconductor layer in a region where the semiconductor element is to be formed.

摘要翻译： 其中感光体元件和半导体元件形成在公共半导体衬底上的半导体器件包括：第一导电类型的衬底; 以及形成在所述基板上的第二导电类型的半导体层; 所述感光体元件由所述基板和所述半导体层构成; 并且在要形成半导体元件的区域中的半导体层下方的位置处设置具有比衬底高的杂质浓度的第一导电类型的杂质浓度区域。

公开(公告)号：US06798001B2

公开(公告)日：2004-09-28

申请号：US09902177

申请日：2001-07-10

申请人： Tomotaka Fujisawa ,  Chihiro Arai

发明人： Tomotaka Fujisawa ,  Chihiro Arai

IPC分类号： H01L31062

CPC分类号： H01L31/11

摘要： A semiconductor device having a photo diode which has substantially the same sensitivity to a plurality of light having different wavelengths, includes a first and a second conductivity type semiconductor layer formed at a surface layer portion of the first conductivity type semiconductor layer, wherein the sensitivity to light of a first wavelength and a second wavelength which is different from the first wavelength, are made substantially the same by designing a region in which a depletion layer spreads from a junction of the first and second conductivity type semiconductor layers and when an inverse bias is applied to the first and second conductivity type semiconductor layers, for example, by designing it to spread in a region of 3 to 6 &mgr;m or a region of 2 to 7 &mgr;m from the surface of the second conductivity type semiconductor layer in the depth direction.

摘要翻译： 具有对具有不同波长的多个光具有基本上相同灵敏度的光电二极管的半导体器件包括形成在第一导电类型半导体层的表层部分的第一和第二导电类型半导体层，其中对 通过设计从第一和第二导电类型半导体层的接合层扩散的耗尽层的区域，并且当反向偏置为 施加到第一和第二导电类型半导体层，例如通过将其设计成在深度方向上从第二导电类型半导体层的表面扩展到3至6μm的区域或2至7μm的区域。

公开(公告)号：US06756280B2

公开(公告)日：2004-06-29

申请号：US10442911

申请日：2003-05-21

申请人： Tomotaka Fujisawa ,  Chihiro Arai

发明人： Tomotaka Fujisawa ,  Chihiro Arai

IPC分类号： H01L218222

CPC分类号： H01L27/075 ,  H01L27/0761

摘要： In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.

摘要翻译： 在具有使用双极型晶体管的结型二极管的半导体器件及其制造方法中，提高了二极管电流与漏电流的比例，并且在不增加处理的情况下提高了闭锁电阻。 形成p型半导体衬底，集电极掩埋区和n型外延层，在n型外延层中形成ap型第一杂质区，在第一杂质区形成n型第二杂质区， +>沉降片，并且形成集电极，在第一和第二杂质区上形成有公共电极。

公开(公告)号：US06445057B1

公开(公告)日：2002-09-03

申请号：US09483913

申请日：2000-01-18

申请人： Tomotaka Fujisawa ,  Chihiro Arai

发明人： Tomotaka Fujisawa ,  Chihiro Arai

IPC分类号： H01L2900

CPC分类号： H01L27/075 ,  H01L27/0761

摘要： In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.

摘要翻译： 在具有使用双极型晶体管的结型二极管的半导体器件及其制造方法中，提高了二极管电流与漏电流的比例，并且在不增加处理的情况下提高了闭锁电阻。 形成p型半导体衬底，集电极掩埋区和n型外延层，在n型外延层中形成ap型第一杂质区，在第一杂质区形成n型第二杂质区，形成N + 形成集电极，在第一和第二杂质区域上形成有公共电极。

公开(公告)号：US20090104731A1

公开(公告)日：2009-04-23

申请号：US12272171

申请日：2008-11-17

申请人： Tomotaka Fujisawa

发明人： Tomotaka Fujisawa

IPC分类号： H01L31/18 ,  H01L21/31

CPC分类号： H01L31/18 ,  H01L31/02161 ,  H01L31/103

摘要： A semiconductor device manufacturing method including a process of forming a silicon oxide film by thermally oxidizing silicon in the atmosphere of oxygen gas or in the atmosphere of mixed gas of oxygen and hydrogen at a temperature of 800° C. or more in the state in which at least the silicon surface serving as a light-receiving portion of a photodiode is exposed, and a process of depositing a silicon nitride film on the silicon oxide film. At least the silicon oxide film and the silicon nitride film are finally left on the surface of the photodiode as an antireflection film.

摘要翻译： 一种半导体器件制造方法，包括在800℃或更高的温度下，在氧气气氛中或在氧气和氢气的混合气体的气氛中热氧化硅来形成氧化硅膜的工艺， 至少露出用作光电二极管的光接收部分的硅表面，以及在氧化硅膜上沉积氮化硅膜的工艺。 至少氧化硅膜和氮化硅膜最终留在作为抗反射膜的光电二极管的表面上。

公开(公告)号：US5622887A

公开(公告)日：1997-04-22

申请号：US323873

申请日：1994-10-17

申请人： Hiroyuki Miwa ,  Mamoru Shinohara ,  Takayuki Gomi ,  Tomotaka Fujisawa

发明人： Hiroyuki Miwa ,  Mamoru Shinohara ,  Takayuki Gomi ,  Tomotaka Fujisawa

IPC分类号： H01L27/06 ,  H01L21/70

CPC分类号： H01L27/0623

摘要： A semiconductor device comprising a MIS structure comprising a first electrically conductive film formed on an oxide film, a second electrically conductive film formed on at least a part of said first electrically conductive film, an insulator film formed on said second electrically conductive film, and a third electrically conductive film formed on said insulator film; and at least one electrode contact portion formed on said first electrically conductive film. A semiconductor device comprising a MIS capacitor having a diffusion layer inside the semiconductor substrate as a lower electrode with a first electrically conductive type being isolated using another diffusion layer having the opposite conductive type, and said another diffusion layer having the opposite conductive type being further isolated using a diffusion layer for isolation having the first conductive type and which is earthed. A BiCMOS semiconductor device comprising a resistor and an impurity source for the emitter and the emitter electrode for the bipolar transistor made of a same conductor layer, and further, a same conductor layer is provided as the contact electrode for the resistor and the gate for the MOS transistor. Also claimed are processes for fabricating the aforementioned semiconductor devices.

摘要翻译： 一种包括MIS结构的半导体器件，包括形成在氧化膜上的第一导电膜，形成在所述第一导电膜的至少一部分上的第二导电膜，形成在所述第二导电膜上的绝缘膜， 形成在所述绝缘膜上的第三导电膜; 以及形成在所述第一导电膜上的至少一个电极接触部分。 一种半导体器件，包括具有扩散层的MIS电容器，该半导体衬底内的扩散层作为具有第一导电类型的下电极，使用具有相反导电类型的另一扩散层来隔离，并且所述另一个具有相反导电类型的扩散层进一步隔离 使用具有第一导电类型并且接地的用于隔离的扩散层。 一种BiCMOS半导体器件，包括电阻器和用于由相同导体层制成的双极晶体管的发射极和发射极的杂质源，并且还提供相同的导体层作为电阻器的接触电极和用于 MOS晶体管 还要求保护的是制造上述半导体器件的工艺。

公开(公告)号：US06858513B2

公开(公告)日：2005-02-22

申请号：US10327834

申请日：2002-12-23

申请人： Tomotaka Fujisawa

发明人： Tomotaka Fujisawa

IPC分类号： H01L27/08 ,  H01L29/94 ,  H01L21/20

CPC分类号： H01L27/0811 ,  H01L27/0805 ,  H01L29/94

摘要： A semiconductor device having an MIS capacitor having a low capacitance value and an MIS capacitor having a high capacitance value formed on the same substrate, and a manufacturing method thereof. The first MIS capacitor consists of a lower conductive material region formed on the substrate, a multilayer dielectric film consisting of a first insulating film, serving as both an interlayer insulating film and a dielectric film, and a second insulating film serving as a dielectric film of the second MIS capacitor, and an upper conductive material film, and the capacitance of the first MIS capacitor is determined by an area of the dielectric film formed by the second insulating film.

摘要翻译： 具有低电容值的MIS电容器和形成在同一衬底上的具有高电容值的MIS电容器的半导体器件及其制造方法。 第一MIS电容器由形成在基板上的下导电材料区域，由用作层间绝缘膜和电介质膜两者的第一绝缘膜构成的多层电介质膜和用作电介质膜的电介质膜的第二绝缘膜 第二MIS电容器和上导电材料膜，并且第一MIS电容器的电容由由第二绝缘膜形成的电介质膜的面积决定。

公开(公告)号：US06649958B2

公开(公告)日：2003-11-18

申请号：US09937358

申请日：2002-02-11

申请人： Tomotaka Fujisawa

发明人： Tomotaka Fujisawa

IPC分类号： H01L27108

CPC分类号： H01L27/0811 ,  H01L27/0805 ,  H01L29/94

摘要： A semiconductor device having an MIS capacitor having a low capacitance value and an MIS capacitor having a high capacitance value, and to a manufacturing method thereof. One MIS capacitor consists of a lower conductive material region formed on the substrate, a multilayer dielectric film consisting of a first insulating film, serving as both an interlayer insulating film and a dielectric film, and a second insulating film serving as a dielectric film of the other MIS capacitor, and an upper conductive material film, and the capacitance of the first MIS capacitor is determined by an area of the dielectric film formed by the second insulating film.

摘要翻译： 具有低电容值的MIS电容器和具有高电容值的MIS电容器的半导体器件及其制造方法。 一个MIS电容器由形成在基板上的下导电材料区域，由用作层间绝缘膜和电介质膜两者的第一绝缘膜构成的多层电介质膜和用作电介质膜的介电膜的第二绝缘膜组成 其他MIS电容器和上导电材料膜，并且第一MIS电容器的电容由由第二绝缘膜形成的电介质膜的面积确定。

公开(公告)号：US08664031B2

公开(公告)日：2014-03-04

申请号：US12272171

申请日：2008-11-17

申请人： Tomotaka Fujisawa

发明人： Tomotaka Fujisawa

IPC分类号： H01L21/00

CPC分类号： H01L31/18 ,  H01L31/02161 ,  H01L31/103

摘要： A semiconductor device manufacturing method including a process of forming a silicon oxide film by thermally oxidizing silicon in the atmosphere of oxygen gas or in the atmosphere of mixed gas of oxygen and hydrogen at a temperature of 800° C. or more in the state in which at least the silicon surface serving as a light-receiving portion of a photodiode is exposed, and a process of depositing a silicon nitride film on the silicon oxide film. At least the silicon oxide film and the silicon nitride film are finally left on the surface of the photodiode as an antireflection film.

摘要翻译： 一种半导体器件制造方法，包括在800℃或更高的温度下，在氧气气氛中或在氧气和氢气的混合气体的气氛中热氧化硅来形成氧化硅膜的工艺， 至少露出用作光电二极管的光接收部分的硅表面，以及在氧化硅膜上沉积氮化硅膜的工艺。 至少氧化硅膜和氮化硅膜最终留在作为抗反射膜的光电二极管的表面上。