公开(公告)号：US07151784B2

公开(公告)日：2006-12-19

申请号：US10196719

申请日：2002-07-17

申请人： Tomoya Sato ,  Kazuhisa Tanaka ,  Norihiko Mizobata

发明人： Tomoya Sato ,  Kazuhisa Tanaka ,  Norihiko Mizobata

IPC分类号： H04J3/02

CPC分类号： H04N5/4401 ,  H04N21/4263 ,  H04N21/4347 ,  H04N21/4424 ,  H04N21/4622

摘要： A demultiplexer circuit which can simultaneously demultiplex plural pieces of input data while minimizing the circuit scale. The demultiplexer circuit includes an input line identification information addition circuit 2 for giving input line identification information to input data which have data identification information and are inputted through plural input lines 1, respectively; a multiplexer 4 for outputting the input data which have been given the input line identification information, respectively, by the input line identification information addition circuit 2 through one common line 5; a filter 6 for filtering the data outputted from the multiplexer 4 on the basis of the input line identification information and the data identification information at one time; and a filter table 7 that contains filtering conditions which are used in the filter 6.

摘要翻译： 解复用器电路，其可以同时解复用多个输入数据，同时最小化电路规模。 解复用器电路包括输入行识别信息添加电路2，用于给输入行识别信息输入具有数据识别信息的输入数据，并分别通过多个输入行1输入; 多路复用器4，用于通过输入行识别信息添加电路2通过一条公共线5分别输出已经被输入输入行识别信息的输入数据; 滤波器6，用于根据输入线识别信息和数据识别信息一次滤波从多路复用器4输出的数据; 以及包含在过滤器6中使用的过滤条件的过滤器表7。

公开(公告)号：US6115434A

公开(公告)日：2000-09-05

申请号：US162298

申请日：1998-09-28

申请人： Norihiko Mizobata ,  Tomohiro Okuno ,  Wakahiko Okazaki ,  Kazuhisa Tanaka

发明人： Norihiko Mizobata ,  Tomohiro Okuno ,  Wakahiko Okazaki ,  Kazuhisa Tanaka

IPC分类号： H04L12/70 ,  H04N5/00 ,  H04N7/08 ,  H04N7/081 ,  H04N7/24 ,  H04N7/52 ,  H04N19/00 ,  H04L27/06

CPC分类号： H04N21/4345 ,  H04N21/235 ,  H04N21/434 ,  H04N21/435 ,  H04N7/52

摘要： A data match detecting apparatus which sequentially receives input data comprising plural fields, comprises parameter storage which contains a parameter group comprising plural parameters which are checked to detect a match between the plural fields and the plural parameters; parameter selector for selecting a parameter corresponding to a field input as the input data from the parameter storage and outputting the selected parameter; data comparator for checking match between the parameter output from the parameter selector and the input data; a comparison result storing circuit initialing its storage content to match before a first field of the input data for which match detection should be performed is input, storing a comparison result of a comparison result decider when there is an input field, and outputting its storage content when all the fields of the input data for which match detection should be performed have been input; and the comparison result decider storing match in the comparison result storage when the storage content of the comparison result storage and the comparison result of the data comparator are match.

摘要翻译： 一种数据匹配检测装置，其顺序地接收包括多个字段的输入数据，包括参数存储器，其包含参数组，所述参数组包括被检查以检测所述多个字段与所述多个参数之间的匹配的多个参数; 参数选择器，用于从参数存储器中选择与场输入对应的参数作为输入数据并输出所选参数; 数据比较器，用于检查参数选择器输出的参数与输入数据之间的匹配; 比较结果存储电路在输入要进行匹配检测的输入数据的第一场之前初始化其存储内容进行匹配，存储当存在输入场时比较结果判定器的比较结果，并输出其存储内容 当输入匹配检测的输入数据的所有字段都被输入时; 并且当比较结果存储的存储内容和数据比较器的比较结果相匹配时，比较结果判定器存储在比较结果存储中。

公开(公告)号：US20120327305A1

公开(公告)日：2012-12-27

申请号：US13604855

申请日：2012-09-06

申请人： Tomokuni YAMAGUCHI ,  Norihiko Mizobata ,  Shirou Yoshioka

发明人： Tomokuni YAMAGUCHI ,  Norihiko Mizobata ,  Shirou Yoshioka

IPC分类号： H04N5/222

CPC分类号： H04N5/44 ,  H04N5/63 ,  H04N21/4436

摘要： In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

摘要翻译： 在视频音频处理装置中，信号处理块（11,12）包括指令存储器（111,121），并根据加载到指令存储器中的程序进行信号处理。 主存储部分（20）具有自刷新功能，并且可从信号处理块访问。 辅助存储部分（30）存储用于使信号处理块执行信号处理的程序。 控制部（15）在接收到备用指示时，以从辅助存储部向主存储部传送程序的方式进行控制，在主存储部中设置自刷新，并且在接收到 返回指令以取消主存储部中的自刷新的方式进行控制，将程序从主存储部加载到信号处理块中的指令存储器，并且激活信号处理块。

公开(公告)号：US08089180B2

公开(公告)日：2012-01-03

申请号：US12282214

申请日：2007-06-29

申请人： Yuka Takahashi ,  Norihiko Mizobata

发明人： Yuka Takahashi ,  Norihiko Mizobata

IPC分类号： H01H35/14 ,  H01H37/00 ,  H01H47/24 ,  H01H47/26

CPC分类号： H01L27/0248 ,  Y10T307/773

摘要： Disclosed is an integrated circuit device comprising a startup operation circuit (101) for carrying out processing necessary for startup and a post-startup operation circuit (102) for carrying out a main operation after completion of the processing necessary for startup, wherein the post-startup operation circuit (102) has an operation guaranteed temperature whose lower limit is higher than a lower limit of an operation guaranteed temperature of the startup operation circuit (101), and the post-startup operation circuit (102) starts the main operation after a temperature of the integrated circuit device exceeds a threshold temperature which is equal to the lower limit of the operation guaranteed temperature of the post-startup operation circuit (102).

摘要翻译： 公开了一种集成电路装置，其包括用于启动启动所需的启动操作电路（101）和用于在完成启动所需的处理之后进行主操作的后启动操作电路（102），其中， 起动运转电路102具有下限比启动运转电路101的运转保证温度的下限高的运转保证温度，而后启动运转电路102在a 集成电路器件的温度超过与启动后操作电路（102）的工作保证温度的下限相等的阈值温度。

公开(公告)号：US07012932B1

公开(公告)日：2006-03-14

申请号：US09339246

申请日：1999-06-24

申请人： Norihiko Mizobata

发明人： Norihiko Mizobata

IPC分类号： H04J1/00 ,  H04K1/00 ,  H04N7/20

CPC分类号： H04N21/435 ,  H04H40/18 ,  H04N5/4401 ,  H04N21/235 ,  H04N21/4263

摘要： A digital broadcast data receiving apparatus comprises a plurality of broadcast data receiving units for receiving digital broadcast data supplied from a plurality of digital broadcast data sources, respectively and a parallel receiving unit for receiving, from the digital broadcast data output from the plural broadcast data receiving units, object program broadcast data which are multiplexed digital broadcast data including program broadcast data relating to an object program broadcast to be viewed by the viewer, and received broadcast data which are digital broadcast data output from the broadcast data receiving unit different from the broadcast data receiving unit which outputs the object program broadcast data. The parallel receiving unit performs the following processes according to time division multiplexing: a process of extracting program broadcast data relating to the object program broadcast to be viewed from the object program broadcast data, and a process of extracting data including information to be obtained even when the viewer does not watch the broadcast, from the received broadcast data. Therefore, it is possible to realize a receiving apparatus Which receives digital broadcast data supplied from plural input sources at the same time, and obtains necessary data included in the digital broadcast data supplied from one of the input sources while displaying the digital broadcast data supplied from the other input source, on a television receiver.

摘要翻译： 数字广播数据接收装置包括分别从多个数字广播数据源接收数字广播数据的多个广播数据接收单元和一个并行接收单元，用于从多个广播数据接收中输出的数字广播数据接收 单元，对象节目广播数据，其是包括与观众要观看的广播目标节目相关的节目广播数据的复用数字广播数据，以及作为从广播数据接收单元输出的不同于广播数据的数字广播数据的接收广播数据 接收单元，其输出对象节目广播数据。 并行接收单元根据时分多路复用进行以下处理：从目标程序广播数据中提取与要广播的对象节目有关的节目广播数据的处理，以及提取包含即使在 观众不会从收到的广播数据中观看广播。 因此，可以实现从多个输入源同时接收的数字广播数据的接收装置，并且从显示从一个输入源提供的数字广播数据的同时获得包括在从一个输入源提供的数字广播数据中的必要数据， 另一个输入源，在电视接收机上。

公开(公告)号：US20050004901A1

公开(公告)日：2005-01-06

申请号：US10880665

申请日：2004-07-01

申请人： Norihiko Mizobata ,  Koichi Tsutsumi

发明人： Norihiko Mizobata ,  Koichi Tsutsumi

IPC分类号： H04N7/08 ,  G06F7/00 ,  H04J3/00 ,  H04N5/00 ,  H04N7/081 ,  H04N7/24 ,  H04N21/434

CPC分类号： H04N21/434

摘要： A first memory stores in advance, in an address assigned to each of possible values that each of the plurality of data segments can have, reference data which indicates that the possible value is consistent with the detection condition (“consistency”) or reference data which indicates that the possible value is inconsistent with the detection condition (“inconsistency”) based on the detection condition. A data extraction section sequentially extracts a data segment from the input data to supply an address corresponding to a value of the extracted data segment to the first memory. The first memory outputs reference data stored in the address supplied from the data extraction section. A determination section determines whether or not the input data is consistent with the detection condition based on the reference data output from the first memory.

摘要翻译： 第一存储器预先存储分配给多个数据段中的每一个可能具有的每个可能值的地址，指示可能值与检测条件（“一致性”）或参考数据一致的参考数据，其中 表示可能的值与基于检测条件的检测条件（“不一致”）不一致。 数据提取部分从输入数据中顺序地提取数据段，以将提取的数据段的值提供给第一存储器。 第一存储器输出存储在从数据提取部分提供的地址中的参考数据。 确定部分基于从第一存储器输出的参考数据来确定输入数据是否与检测条件一致。

公开(公告)号：US5524197A

公开(公告)日：1996-06-04

申请号：US944385

申请日：1992-09-14

申请人： Masaru Uya ,  Norihiko Mizobata ,  Takuya Sayama ,  Satoshi Takahashi ,  Takeshi Ichise ,  Takeshi Kawano ,  Taizo Tsujimoto

发明人： Masaru Uya ,  Norihiko Mizobata ,  Takuya Sayama ,  Satoshi Takahashi ,  Takeshi Ichise ,  Takeshi Kawano ,  Taizo Tsujimoto

IPC分类号： G06F3/14 ,  G06F3/048 ,  G06F3/153 ,  G06T3/00 ,  G06T11/00 ,  G06T13/00 ,  G06T13/20 ,  G06T13/80 ,  G09G5/06 ,  G09G5/14 ,  G09G5/36 ,  G06F15/00

CPC分类号： G09G5/14 ,  G06T11/00 ,  G09G5/06 ,  G09G2340/125

摘要： A dynamic-image displaying workstation provided with a display device for displaying an image, a video signal processing circuit for outputting dynamic-image data representing a dynamic image corresponding to a video signal, a first dual port memory for receiving and storing the dynamic-image data outputted from the video signal processing circuit, a second dual port memory for storing data representing pixels of an image to be displayed by the display device, and a third dual port memory for storing data representing a window area. The window area is an area of a window, to which the dynamic-image belongs, and is not covered by any other windows. The workstation is further provided with a fourth dual port memory for storing data representing a dynamic-image display effective area corresponding to the dynamic image represented by the dynamic-image stored in the first dual port memory, a data selector for receiving data read from the first dual port memory at a first input terminal thereof, and data read from the second dual port memory at a second input terminal thereof, for selecting one of the third and fourth dual port memories and receiving data read from the selected dual port memory at a third input terminal thereof, for selecting the data received at the first input terminal thereof if the data read from the third dual port memory is the data representing the window area, and the data read from the third dual port memory is the data representing the dynamic-image display effective area, for selecting the data received at the second input terminal thereof and for outputting a signal representing the selected data to the display device.

摘要翻译： 一种具有显示图像的显示装置的动态图像显示工作站，用于输出表示对应于视频信号的动态图像的动态图像数据的视频信号处理电路，用于接收和存储动态图像的第一双端口存储器 从视频信号处理电路输出的数据，用于存储表示要由显示装置显示的图像的像素的数据的第二双端口存储器，以及用于存储表示窗口区域的数据的第三双端口存储器。 窗口区域是动态图像所属的窗口区域，不被任何其他窗口覆盖。 该工作站还设置有第四双端口存储器，用于存储表示与由存储在第一双端口存储器中的动态图像表示的动态图像相对应的动态图像显示有效区域的数据，用于接收从第一双端口存储器读取的数据的数据选择器 在其第一输入端处的第一双端口存储器，以及在其第二输入端从第二双端口存储器读取的数据，用于选择第三和第四双端口存储器中的一个并且接收从所选择的双端口存储器读取的数据 如果从第三双端口存储器读取的数据是表示窗口区域的数据，并且从第三双端口存储器读取的数据是表示动态的数据的数据，则用于选择在其第一输入端子接收的数据 - 图像显示有效区域，用于选择在其第二输入端接收的数据，并将表示所选数据的信号输出到di 喷射装置

公开(公告)号：US07359441B2

公开(公告)日：2008-04-15

申请号：US10467448

申请日：2002-03-27

申请人： Mikihiko Yamada ,  Shouichi Gotoh ,  Norihiko Mizobata

发明人： Mikihiko Yamada ,  Shouichi Gotoh ,  Norihiko Mizobata

IPC分类号： H04N7/18

CPC分类号： H04N21/4385 ,  H04N21/23608 ,  H04N21/434 ,  H04N21/4344 ,  H04N21/4345 ,  H04N21/4347

摘要： In a packet data processing determination apparatus (DBA1) for respectively and sequentially determining a plurality of packet data (P) composing an inputted transport stream (TS), a packet data storage section (270) stores the packet data (P) for a predetermined time period in the order in which they came. A stored packet data identifying section (270, 260) reads identification information (PIDe) from the stored packet data (P). A target packet data determining section (400) compares the read identification information (PIDe) with predetermined process information (PIDd) to determine whether the packet data (P) is to be processed.

摘要翻译： 在分组数据处理确定装置（DBA 1）中，分组数据存储部分（270）分别存储用于组合输入的传输流（TS）的多个分组数据（P） 预定时间段，以他们来的顺序。 存储的分组数据识别部分（270,260）从存储的分组数据（P）读取识别信息（PIDe）。 目标分组数据确定部分（400）将读取的识别信息（PIDe）与预定的处理信息（PIDd）进行比较，以确定分组数据（P）是否被处理。

公开(公告)号：US20060184780A1

公开(公告)日：2006-08-17

申请号：US10548290

申请日：2004-04-16

申请人： Mikihiko Yamada ,  Norihiko Mizobata ,  Taku Arakawa

发明人： Mikihiko Yamada ,  Norihiko Mizobata ,  Taku Arakawa

IPC分类号： G06F15/177

CPC分类号： G06F9/4403

摘要： With a temporary operating unit being operating, a user provides a boot timing using a boot timing instructing unit. This causes a CPU to compute a boot preparation timing based on the boot timing, and store the boot timing and boot preparation timing to a boot timing memory. At this time, a timer begins a time-keeping operation. After that, the user turns off the power to the temporary operating unit. A boot preparation instructing unit determines whether or not the time being measured by the timer coincides with the boot preparation timing stored in the boot timing memory. When the time measured by the timer coincides with the boot preparation timing stored in the boot timing memory, the boot preparation instructing unit provides the CPU with a boot preparation instruction. This turns on the power to the temporary operating unit, and the CPU performs a boot preparation.

摘要翻译： 在操作临时操作单元的情况下，用户使用引导定时指令单元提供启动定时。 这导致CPU基于引导定时计算引导准备定时，并将引导定时和引导准备时序存储到引导定时存储器。 此时，定时器开始计时操作。 之后，用户关闭临时操作单元的电源。 引导准备指示单元确定定时器测量的时间是否与存储在引导定时存储器中的引导准备定时一致。 当由定时器测量的时间与存储在引导定时存储器中的引导准备定时一致时，引导准备指令单元向CPU提供引导准备指令。 这将打开临时操作单元的电源，并且CPU执行启动准备。

公开(公告)号：US07054989B2

公开(公告)日：2006-05-30

申请号：US10210096

申请日：2002-08-02

申请人： Norihiko Mizobata

发明人： Norihiko Mizobata

IPC分类号： G06F13/00

CPC分类号： H04N5/765 ,  H04N5/775

摘要： The stream processor of the present invention includes: a selection section and first to fifth processing sections. In the selection section, a plurality of inputs are associated with a plurality of outputs according to control from outside so that streams sent to the plurality of inputs are passed to the associated outputs. The first processing section sends a first stream to the first input among the plurality of inputs. The second processing section sends a second stream to the second input among the plurality of inputs. The third processing section receives a stream from the first output among the plurality of outputs. The fourth processing section receives a stream from the second output among the plurality of outputs. The fifth processing section receives a stream from the third output among the plurality of outputs, subjects the received stream to predetermined processing, and sends the processed stream to the third input among the plurality of inputs.