-
公开(公告)号：US08723291B2
公开(公告)日：2014-05-13
申请号：US13592949
申请日：2012-08-23
IPC分类号： H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first the via hole wiring is surrounded.
摘要翻译： 一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。 半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 保险丝布线被超过预定值的电流切断。 第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中 层。 在熔丝配线中，在第一通孔配线的外侧形成有一对的第二通孔配线，以使第一通孔配线被包围。
-
2.发明授权Semiconductor device having electrical fuses with less power consumption and interconnection arrangement 有权具有电功率消耗较小的电熔丝和互连配置的半导体器件公开(公告)号：US08331185B2
公开(公告)日：2012-12-11
申请号：US12723218
申请日：2010-03-12
申请人： Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
发明人： Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/027 , G11C29/028 , G11C29/785 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The fuse program circuit provided with fuse elements that can be programmed even after packaging is implemented with low power consumption and a low occupation area.
摘要翻译： 在熔丝编程电路中，使用第三层或更高层多层金属互连的金属互连实施熔丝元件FS。 在每个熔丝编程电路中，使用扫描触发器顺序传送程序信息和熔丝选择信息，并且一个接一个地选择性地电熔熔断器。 设置有即使在封装之后也可以被编程的熔丝元件的保险丝编程电路以低功耗和低占用面积实现。
-
3.发明授权Semiconductor device having electrical fuses with less power consumption and interconnection arrangement 有权具有电功率消耗较小的电熔丝和互连配置的半导体器件公开(公告)号：US07706202B2
公开(公告)日：2010-04-27
申请号：US11802627
申请日：2007-05-24
申请人： Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
发明人： Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/027 , G11C29/028 , G11C29/785 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The fuse program circuit provided with fuse elements that can be programmed even after packaging is implemented with low power consumption and a low occupation area.
摘要翻译： 在熔丝编程电路中，使用第三层或更高层多层金属互连的金属互连实施熔丝元件FS。 在每个熔丝编程电路中，使用扫描触发器顺序传送程序信息和熔丝选择信息，并且一个接一个地选择性地电熔熔断器。 设置有即使在封装之后也可以被编程的熔丝元件的保险丝编程电路以低功耗和低占用面积实现。
-
公开(公告)号：US20070280012A1
公开(公告)日：2007-12-06
申请号：US11802627
申请日：2007-05-24
申请人： Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
发明人： Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
CPC分类号： G11C17/18 , G11C17/165 , G11C29/027 , G11C29/028 , G11C29/785 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The fuse program circuit provided with fuse elements that can be programmed even after packaging is implemented with low power consumption and a low occupation area.
摘要翻译： 在熔丝编程电路中，使用第三层或更高层多层金属互连的金属互连实施熔丝元件FS。 在每个熔丝编程电路中，使用扫描触发器顺序传送程序信息和熔丝选择信息，并且一个接一个地选择性地电熔熔断器。 设置有即使在封装之后也可以被编程的熔丝元件的保险丝编程电路以低功耗和低占用面积实现。
-
5.发明申请公开(公告)号：US20070210414A1
公开(公告)日：2007-09-13
申请号：US11683053
申请日：2007-03-07
CPC分类号： H01L23/5256 , H01H85/041 , H01L23/5227 , H01L23/525 , H01L23/528 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
摘要翻译： 提供一种具有电熔丝结构的半导体器件，其接收要被允许切割的电流的供应，而不损坏保险丝周围的部分。 电子熔断器电连接在电子电路和冗余电路之间，作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。
-
公开(公告)号：US20130049166A1
公开(公告)日：2013-02-28
申请号：US13592949
申请日：2012-08-23
IPC分类号： H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by a current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, a second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first via hole wiring is surrounded.
摘要翻译： 一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。 半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 保险丝布线被超过预定值的电流切断。 第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中 层。 在保险丝布线中，在第一通孔布线的外侧形成有一对第二通孔布线，使得第一通孔布线被包围。
-
7.发明授权公开(公告)号：US07745905B2
公开(公告)日：2010-06-29
申请号：US11683053
申请日：2007-03-07
IPC分类号： H01L29/86
CPC分类号： H01L23/5256 , H01H85/041 , H01L23/5227 , H01L23/525 , H01L23/528 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
摘要翻译： 提供一种具有电熔丝结构的半导体器件，其接收要被允许切割的电流的供应，而不损坏保险丝周围的部分。 电子熔断器电连接在电子电路和冗余电路之间，作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。
-
公开(公告)号：US20080237787A1
公开(公告)日：2008-10-02
申请号：US11836609
申请日：2007-08-09
IPC分类号： H01L23/48
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention aims at offering the semiconductor integrated circuit which can perform reliable relief processing using an electric fuse.The present invention is provided with a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. And a fuse wiring is cut by passing beyond a predetermined current value. A first electrode pad is connected to one side of a fuse wiring. A second electrode pad is connected to the other of a fuse wiring. A pollution-control layer is formed in the upper layer and the lower layer of a fuse wiring via an insulating layer. It is formed via an insulating layer to the side surface of a fuse wiring, it connects with a pollution-control layer, and the first via hole wiring of a pair surrounds a fuse wiring. To a fuse wiring, the second via hole wiring of a pair is formed in the outside of a first via hole wiring so that a first via hole wiring may be surrounded.
摘要翻译： 本发明的目的在于提供一种使用电熔丝进行可靠的浮雕处理的半导体集成电路。 本发明提供一种熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 并且通过超过预定电流值来切断熔丝布线。 第一电极焊盘连接到熔丝布线的一侧。 第二电极焊盘连接到熔丝布线中的另一个。 通过绝缘层在熔丝布线的上层和下层形成污染控制层。 它通过绝缘层形成在熔丝布线的侧面，它与污染控制层相连，一对第一通孔布线围绕熔丝布线。 对于熔丝布线，一对的第二通孔布线形成在第一通孔布线的外侧，使得可以包围第一通孔布线。
-
公开(公告)号：US20100320562A1
公开(公告)日：2010-12-23
申请号：US12869323
申请日：2010-08-26
IPC分类号： H01L29/86
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.
摘要翻译： 提供具有小占用面积的电直线状熔断器的半导体器件。 多个突出部10f形成在从电熔丝部10a的中间位置偏离的位置，更具体地，形成在远离通孔10e和靠近通孔10d的位置。 多个突出部20f形成在从电熔丝部20a的中间位置偏移的位置，更具体地，形成在远离通孔20d和靠近20e的位置。 也就是说，突出部分10f和突出部分20f被布置成Z字形。
-
公开(公告)号：US20080164969A1
公开(公告)日：2008-07-10
申请号：US11958360
申请日：2007-12-17
IPC分类号： H01H37/76
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.
摘要翻译： 提供具有小占用面积的电直线状熔断器的半导体器件。 多个突出部分10f形成在从电熔丝部分10a的中间位置偏移的位置，更具体地，形成在远离通孔10e和靠近通孔10d的位置。 多个突出部分20f形成在从电熔丝部分20a的中间位置移位的位置，更具体地，形成在远离通孔20d和靠近20e的位置。 也就是说，突出部分10f和突出部分20f被布置成Z字形。
-
-
-
-
-
-
-
-
-
搜索结果
25 条记录 (耗时 0.023 秒)
