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    SEMICONDUCTOR INTEGRATED CIRCUIT
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20130049166A1

    公开(公告)日：2013-02-28

    申请号：US13592949

    申请日：2012-08-23

    申请人： Toshiaki YONEZU ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    发明人： Toshiaki YONEZU ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    IPC分类号： H01L23/62

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by a current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, a second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first via hole wiring is surrounded.

    摘要翻译： 一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。 半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 保险丝布线被超过预定值的电流切断。 第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中 层。 在保险丝布线中，在第一通孔布线的外侧形成有一对第二通孔布线，使得第一通孔布线被包围。

    Semiconductor device and a method of increasing a resistance value of an electric fuse
    2.
    发明授权
    Semiconductor device and a method of increasing a resistance value of an electric fuse 有权
    半导体器件和增加电熔丝电阻值的方法

    公开(公告)号：US07745905B2

    公开(公告)日：2010-06-29

    申请号：US11683053

    申请日：2007-03-07

    申请人： Takeshi Iwamoto ,  Kazushi Kono ,  Masashi Arakawa ,  Toshiaki Yonezu ,  Shigeki Obayashi

    发明人： Takeshi Iwamoto ,  Kazushi Kono ,  Masashi Arakawa ,  Toshiaki Yonezu ,  Shigeki Obayashi

    IPC分类号： H01L29/86

    CPC分类号： H01L23/5256 ,  H01H85/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

    摘要翻译： 提供一种具有电熔丝结构的半导体器件，其接收要被允许切割的电流的供应，而不损坏保险丝周围的部分。 电子熔断器电连接在电子电路和冗余电路之间，作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20080237787A1

    公开(公告)日：2008-10-02

    申请号：US11836609

    申请日：2007-08-09

    申请人： Toshiaki Yonezu ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    发明人： Toshiaki Yonezu ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention aims at offering the semiconductor integrated circuit which can perform reliable relief processing using an electric fuse.The present invention is provided with a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. And a fuse wiring is cut by passing beyond a predetermined current value. A first electrode pad is connected to one side of a fuse wiring. A second electrode pad is connected to the other of a fuse wiring. A pollution-control layer is formed in the upper layer and the lower layer of a fuse wiring via an insulating layer. It is formed via an insulating layer to the side surface of a fuse wiring, it connects with a pollution-control layer, and the first via hole wiring of a pair surrounds a fuse wiring. To a fuse wiring, the second via hole wiring of a pair is formed in the outside of a first via hole wiring so that a first via hole wiring may be surrounded.

    摘要翻译： 本发明的目的在于提供一种使用电熔丝进行可靠的浮雕处理的半导体集成电路。 本发明提供一种熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 并且通过超过预定电流值来切断熔丝布线。 第一电极焊盘连接到熔丝布线的一侧。 第二电极焊盘连接到熔丝布线中的另一个。 通过绝缘层在熔丝布线的上层和下层形成污染控制层。 它通过绝缘层形成在熔丝布线的侧面，它与污染控制层相连，一对第一通孔布线围绕熔丝布线。 对于熔丝布线，一对的第二通孔布线形成在第一通孔布线的外侧，使得可以包围第一通孔布线。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US08723291B2

    公开(公告)日：2014-05-13

    申请号：US13592949

    申请日：2012-08-23

    申请人： Toshiaki Yonezu ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    发明人： Toshiaki Yonezu ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    IPC分类号： H01L23/62

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first the via hole wiring is surrounded.

    摘要翻译： 一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。 半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 保险丝布线被超过预定值的电流切断。 第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中 层。 在熔丝配线中，在第一通孔配线的外侧形成有一对的第二通孔配线，以使第一通孔配线被包围。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    10.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20130049864A1

    公开(公告)日：2013-02-28

    申请号：US13589369

    申请日：2012-08-20

    申请人： Natsuki IKEHATA ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    发明人： Natsuki IKEHATA ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    IPC分类号： H03F3/45

    CPC分类号： G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

    摘要翻译： 差分放大电路的输出信号特性得到改善。 当输入数据信号为低电平时，流过第一晶体管的电流将减小，并且第一电阻器和第二电阻器之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为高电平时，第一晶体管的电流增加，因此节点处的电位降低。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。