公开(公告)号：US10481975B2

公开(公告)日：2019-11-19

申请号：US15699200

申请日：2017-09-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Daisuke Saida ,  Hiroki Noguchi ,  Keiko Abe ,  Shinobu Fujita

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/16 ,  G11C29/52 ,  G11C29/02 ,  G11C29/44 ,  G11C29/04

Abstract: A memory system has a non-volatile memory, an error corrector, an error information storage, and an access controller. The non-volatile memory comprising a plurality of memory cells. The error corrector to correct an error included in data read from the non-volatile memory. The error information storage, based on an error rate when a predetermined number or more of data is written in the non-volatile memory and read therefrom, to store first information on whether there is an error in the written data, on whether there is an error correctable by the error corrector in the written data, and on whether there is an error uncorrectable by the error corrector in the written data. The access controller, based on the first information, to control at least one of reading from or writing to the non-volatile memory.

公开(公告)号：US10141038B2

公开(公告)日：2018-11-27

申请号：US15703438

申请日：2017-09-13

Applicant: Toshiba Memory Corporation

Inventor： Kazutaka Ikegami ,  Hiroki Noguchi ,  Keiko Abe

IPC: G11C11/16

Abstract: According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array; a processor configured to receive a first data from the device, the first data from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data from the selected region by the second read operation.

公开(公告)号：US20180277187A1

公开(公告)日：2018-09-27

申请号：US15703438

申请日：2017-09-13

Applicant: Toshiba Memory Corporation

Inventor： Kazutaka Ikegami ,  Hiroki Noguchi ,  Keiko Abe

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0057

Abstract: According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array; a processor configured to receive a first data from the device, the first data from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data from the selected region by the second read operation.