公开(公告)号：US20180006042A1

公开(公告)日：2018-01-04

申请号：US15708033

申请日：2017-09-18

Applicant: Toshiba Memory Corporation

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11575 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L21/823437 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20210217755A1

公开(公告)日：2021-07-15

申请号：US17214710

申请日：2021-03-26

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L21/8234

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20190164979A1

公开(公告)日：2019-05-30

申请号：US16262827

申请日：2019-01-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/8234 ,  H01L27/11575

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20200212053A1

公开(公告)日：2020-07-02

申请号：US16815852

申请日：2020-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L21/8234

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20180358368A1

公开(公告)日：2018-12-13

申请号：US16104843

申请日：2018-08-17

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/8234 ,  H01L27/11575

CPC classification number: H01L27/1157 ,  H01L21/823437 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.