公开(公告)号：US20210217755A1

公开(公告)日：2021-07-15

申请号：US17214710

申请日：2021-03-26

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L21/8234

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20190164979A1

公开(公告)日：2019-05-30

申请号：US16262827

申请日：2019-01-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/8234 ,  H01L27/11575

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20180337194A1

公开(公告)日：2018-11-22

申请号：US16047811

申请日：2018-07-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Yoshihisa IWATA

IPC: H01L27/11582 ,  H01L29/792 ,  G11C5/06 ,  H01L27/11575 ,  H01L27/11568 ,  G11C7/18 ,  H01L23/528 ,  G11C5/02 ,  G11C16/04 ,  G11C8/12 ,  H01L27/10 ,  G11C5/04

CPC classification number: H01L27/11582 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/18 ,  G11C8/12 ,  G11C16/0483 ,  G11C2213/71 ,  H01L23/528 ,  H01L27/10 ,  H01L27/11568 ,  H01L27/11575 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

公开(公告)号：US20180006042A1

公开(公告)日：2018-01-04

申请号：US15708033

申请日：2017-09-18

Applicant: Toshiba Memory Corporation

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11575 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L21/823437 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20200212053A1

公开(公告)日：2020-07-02

申请号：US16815852

申请日：2020-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L21/8234

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20180358368A1

公开(公告)日：2018-12-13

申请号：US16104843

申请日：2018-08-17

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/8234 ,  H01L27/11575

CPC classification number: H01L27/1157 ,  H01L21/823437 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.