公开(公告)号：US20200090751A1

公开(公告)日：2020-03-19

申请号：US16692374

申请日：2019-11-22

Applicant: Toshiba Memory Corporation

Inventor： Takashi KOBAYASHI ,  Yoichi MINEMURA ,  Eietsu TAKAHASHI ,  Masaki KONDO ,  Daisuke HAGISHIMA

IPC: G11C16/04 ,  G11C16/32 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11529 ,  G06F3/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/24

Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.