公开(公告)号：US20200090751A1

公开(公告)日：2020-03-19

申请号：US16692374

申请日：2019-11-22

Applicant: Toshiba Memory Corporation

Inventor： Takashi KOBAYASHI ,  Yoichi MINEMURA ,  Eietsu TAKAHASHI ,  Masaki KONDO ,  Daisuke HAGISHIMA

IPC: G11C16/04 ,  G11C16/32 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11529 ,  G06F3/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/24

Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.

公开(公告)号：US20200303404A1

公开(公告)日：2020-09-24

申请号：US16560416

申请日：2019-09-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoichi MINEMURA ,  Michiaki MATSUO ,  Reiko SHAMOTO

IPC: H01L27/11582 ,  H01L27/11573 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11565 ,  G11C16/04 ,  G11C16/08

Abstract: According to one embodiment, in a semiconductor storage device, a peripheral circuit supplies a first voltage to a second region when supplying a select potential to a region corresponding to the second region, in a second conductive layer. The peripheral circuit supplies a second voltage higher than the first voltage to a first region when supplying a select potential to a region corresponding to the first region, in the second conductive layer.

公开(公告)号：US20180261615A1

公开(公告)日：2018-09-13

申请号：US15700408

申请日：2017-09-11

Applicant: Toshiba Memory Corporation

Inventor： Yoichi MINEMURA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes a stacked body, a first semiconductor member, a first insulating layer, a second semiconductor member, and a second insulating layer. The stacked body includes an electrode film and an insulating film arranged alternately along a first direction. The first and second semiconductor members extend in the first direction and pierce the electrode film and the insulating film. The first insulating layer contacts the insulating film and is provided at a periphery of the first semiconductor member. The second insulating layer contacts the insulating film and is provided at a periphery of the second semiconductor member. The first insulating layer is thicker than the second insulating layer. A major diameter of the first semiconductor member is smaller than a major diameter of the second semiconductor member when viewed from the first direction.

公开(公告)号：US20200303396A1

公开(公告)日：2020-09-24

申请号：US16565588

申请日：2019-09-10

Applicant: Toshiba Memory Corporation

Inventor： Yoichi MINEMURA

IPC: H01L27/11578 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526

Abstract: According to one embodiment, in a semiconductor storage device, the first contact plug electrically connects the third region to the first drive circuit. The second contact plug is provided on one end side of a fourth region in the third direction, the fourth region arranged between the first separation film and the second separation film in the second conductive layer. The second contact plug electrically connects the fourth region to the first drive circuit. The third contact plug is provided on the other end side of the third region in the third direction. The third contact plug electrically connects the third region to the second drive circuit.

公开(公告)号：US20190287989A1

公开(公告)日：2019-09-19

申请号：US16109381

申请日：2018-08-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaharu MIZUTANI ,  Yoichi MINEMURA

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/78

Abstract: A semiconductor device includes a base, a stacked body, a plate-shaped portion, and first to third columnar portions. The stacked body is provided over the base. The plate-shaped portion is inside the stacked body from an upper end of the stacked body to the base. The first to third columnar portions are inside the stacked body from the upper end of the stacked body to the base. The second columnar portion is located away from the first columnar portion in a first direction. The third columnar portion is aligned with the first columnar portion and the second columnar portion in the first direction. A pitch between the third columnar portion and the first columnar portion is a first pitch. A pitch between the third columnar portion and the second columnar portion is a second pitch larger than the first pitch.

公开(公告)号：US20180277221A1

公开(公告)日：2018-09-27

申请号：US15907286

申请日：2018-02-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoichi MINEMURA

IPC: G11C16/10 ,  H01L23/528 ,  H01L29/10 ,  H01L27/11568 ,  H01L29/08 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device includes stacked word lines stacked and a semiconductor channel passing through the word lines in a first direction. Memory cells are disposed along the semiconductor channel in the first direction. Each memory cell includes a charge retention film between the semiconductor channel and a respective word line in the plurality of word lines. A controller is connected to the semiconductor channel and the word lines and configured to apply a program voltage during a program operation to a memory cell at a potential that increases in voltage steps, and a voltage increment between the voltage steps decreases during the program operation. The increment voltage is changed by the controller depending on a position of the memory cell along the semiconductor channel in the first direction.