-
公开(公告)号：US20190108885A1
公开(公告)日：2019-04-11
申请号：US16209520
申请日：2018-12-04
Applicant: Toshiba Memory Corporation
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
-
公开(公告)号：US20180197616A1
公开(公告)日：2018-07-12
申请号：US15915129
申请日：2018-03-08
Applicant: Toshiba Memory Corporation
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
CPC classification number: G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3427 , G11C16/349
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
-
公开(公告)号：US20210217481A1
公开(公告)日：2021-07-15
申请号：US17219003
申请日：2021-03-31
Applicant: Toshiba Memory Corporation
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
-
4.发明申请公开(公告)号：US20200090751A1
公开(公告)日：2020-03-19
申请号：US16692374
申请日：2019-11-22
Applicant: Toshiba Memory Corporation
Inventor： Takashi KOBAYASHI , Yoichi MINEMURA , Eietsu TAKAHASHI , Masaki KONDO , Daisuke HAGISHIMA
IPC: G11C16/04 , G11C16/32 , G11C16/10 , G11C11/56 , H01L27/11529 , G06F3/06 , G11C16/08 , G11C16/16 , G11C16/28 , G11C16/24
Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.
-
Patent Agency Ranking
公开(公告)号：US20190287640A1
公开(公告)日：2019-09-19
申请号：US16109343
申请日：2018-08-22
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Eietsu TAKAHASHI
Abstract: A memory system includes a nonvolatile memory which includes a memory cell array, and a memory controller which includes a first ECC circuit, and a second ECC circuit having an error correction capability higher than that of the first ECC circuit, and is configured to perform ECC operation on data read from the nonvolatile memory using the first ECC circuit and the ECC circuit. During the ECC operation, the first ECC circuit corrects an error in first read data which is read out of the nonvolatile memory. The memory controller determines whether the hard error occurs in the memory cell array in a case where the first ECC circuit is unable to correct the error. In a case where the hard error occurs, the second ECC circuit performs error correction using second read data that excludes a bit where the hard error occurs.
-
公开(公告)号：US20210020249A1
公开(公告)日：2021-01-21
申请号：US17064053
申请日：2020-10-06
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI
Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
-
公开(公告)号：US20210005270A1
公开(公告)日：2021-01-07
申请号：US17026904
申请日：2020-09-21
Applicant: Toshiba Memory Corporation
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
-
公开(公告)号：US20180308550A1
公开(公告)日：2018-10-25
申请号：US16025429
申请日：2018-07-02
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI
CPC classification number: G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
-
公开(公告)号：US20180005695A1
公开(公告)日：2018-01-04
申请号：US15706250
申请日：2017-09-15
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI
CPC classification number: G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.013 seconds)
