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    Semiconductor memory device and production method thereof
    2.
    发明授权
    Semiconductor memory device and production method thereof 有权

    公开(公告)号：US10147735B2

    公开(公告)日：2018-12-04

    申请号：US14849743

    申请日：2015-09-10

    Applicant: Toshiba Memory Corporation

    Inventor： Tadashi Iguchi ,  Murato Kawai ,  Toru Matsuda ,  Hisashi Kato ,  Megumi Ishiduki

    IPC: H01L29/792 ,  H01L29/788 ,  H01L27/11582 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11565

    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10510764B2

    公开(公告)日：2019-12-17

    申请号：US15948057

    申请日：2018-04-09

    Applicant: Toshiba Memory Corporation

    Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Toru Matsuda ,  Yu Hirotsu ,  Naoki Yamamoto

    IPC: H01L27/115 ,  H01L21/288 ,  H01L21/768 ,  H01L23/528 ,  H01L29/792 ,  H01L23/498 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

    Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.

    SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF 审中-公开

    公开(公告)号：US20190074294A1

    公开(公告)日：2019-03-07

    申请号：US16183389

    申请日：2018-11-07

    Applicant: Toshiba Memory Corporation

    Inventor： Tadashi IGUCHI ,  Murato Kawai ,  Toru Matsuda ,  Hisashi Kato ,  Megumi Ishiduki

    IPC: H01L27/11582 ,  H01L27/11575 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565

    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190096899A1

    公开(公告)日：2019-03-28

    申请号：US15948057

    申请日：2018-04-09

    Applicant: Toshiba Memory Corporation

    Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Toru Matsuda ,  Yu Hirotsu ,  Naoki Yamamoto

    IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.

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