公开(公告)号：US20190267097A1

公开(公告)日：2019-08-29

申请号：US16114182

申请日：2018-08-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yusuke HIGASHI ,  Tomoya SANUKI

IPC: G11C16/26 ,  H01L27/102 ,  H01L27/11582 ,  G11C16/04 ,  G11C11/56

Abstract: A semiconductor memory device includes an n-type semiconductor region, first to fourth conductive layers above the n-type semiconductor region, a p-type semiconductor region, a semiconductor layer between the n-type semiconductor region and the p-type semiconductor region and extending through the conductive layers, charge storage regions between the conductive layers and the semiconductor layer, a control circuit that executes a first read sequence and a second read sequence following the first read sequence, a comparison circuit that compares the first data read in the first read sequence to the second data read in the second read sequence, and a determination circuit that selects one of the first data and the second data as a true read value. The first and second read sequences each have an off step and an off voltage applied during the first read sequence is different from an off voltage applied during the second read sequence.

公开(公告)号：US20200091174A1

公开(公告)日：2020-03-19

申请号：US16283627

申请日：2019-02-22

Applicant: Toshiba Memory Corporation

Inventor： Tomoya SANUKI ,  Yusuke HIGASHI ,  Hideto HORII ,  Masaki KONDO ,  Hiroki TOKUHIRA ,  Hideaki AOCHI

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/26 ,  G11C16/16

Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.

公开(公告)号：US20190198111A1

公开(公告)日：2019-06-27

申请号：US16122105

申请日：2018-09-05

Applicant: Toshiba Memory Corporation

Inventor： Yusuke HIGASHI

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C7/08

CPC classification number: G11C16/08 ,  G11C7/08 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34

Abstract: According to one embodiment, a semiconductor storage device includes: a first select transistor connected at a first end of a memory string; a second select transistor connected at a second end of the memory string; and a controller. In a write operation of writing data into a first memory cell transistor of the memory string, the controller performs: a first operation of applying a first voltage to a gate of the first memory cell transistor, while turning on the first and second select transistor;and a second operation of applying a second voltage higher than the first voltage to the gate of the first memory cell transistor, while turning off the first and second select transistor; and the second operation is performed after the first operation.