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    WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES
    2.
    发明申请
    WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES 失效
    用于CMOS器件的绝缘隔离（WIT）

    公开(公告)号：US20070241408A1

    公开(公告)日：2007-10-18

    申请号：US11759981

    申请日：2007-06-08

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

    摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

    摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods
    3.
    发明申请
    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods 审中-公开
    用于制造具有降低的对闩锁敏感性的半导体器件结构和通过该方法形成的半导体器件结构的方法

    公开(公告)号：US20070194403A1

    公开(公告)日：2007-08-23

    申请号：US11360345

    申请日：2006-02-23

    申请人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    发明人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L21/76

    CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

    摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体方法和器件结构。 该方法包括在衬底的半导体材料中形成沟槽，其第一侧壁设置在也在衬底的半导体材料中定义的一对掺杂阱之间。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩蔽沟槽的基底，随后去除暴露在部分屏蔽的基底上的衬底的半导体材料，以限定加深沟槽的变窄的第二侧壁。 加深的沟槽填充有介电材料以限定用于内置于掺杂阱中的器件的沟槽隔离区域。 填充沟槽加深的介质材料增强了闩锁抑制。

    Methods and semiconductor structures for latch-up suppression using a conductive region
    4.
    发明申请
    Methods and semiconductor structures for latch-up suppression using a conductive region 失效
    使用导电区域进行闩锁抑制的方法和半导体结构

    公开(公告)号：US20070170543A1

    公开(公告)日：2007-07-26

    申请号：US11340752

    申请日：2006-01-26

    申请人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0921 ,  H01L21/823878 ,  H01L29/78

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 半导体结构包括形成在衬底的半导体材料中的第一和第二相邻的掺杂阱。 在第一和第二掺杂阱之间的衬底中限定了包括基底和基底与顶表面之间的第一侧壁的沟槽。 沟槽部分地填充有与第一和第二掺杂阱电耦合的导体材料。 可以在与沟槽中的导电材料相邻的位置处与沟槽邻接的半导体材料中提供高度掺杂的导电区域。

    Methods and semiconductor structures for latch-up suppression using a buried conductive region
    6.
    发明申请
    Methods and semiconductor structures for latch-up suppression using a buried conductive region 失效
    使用掩埋导电区域进行闩锁抑制的方法和半导体结构

    公开(公告)号：US20070158755A1

    公开(公告)日：2007-07-12

    申请号：US11330689

    申请日：2006-01-12

    申请人： Shunhua Chang ,  Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Shunhua Chang ,  Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0921 ,  H01L21/823878

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁接壤的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。

    CMOS devices adapted to reduce latchup and methods of manufacturing the same
    10.
    发明申请
    CMOS devices adapted to reduce latchup and methods of manufacturing the same 审中-公开
    适于减少闭锁的CMOS器件及其制造方法

    公开(公告)号：US20070170517A1

    公开(公告)日：2007-07-26

    申请号：US11340342

    申请日：2006-01-26

    申请人： Toshiharu Furukawa ,  Charles Koburger ,  Jack Mandelman

    发明人： Toshiharu Furukawa ,  Charles Koburger ,  Jack Mandelman

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76237 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/1087 ,  H01L29/78

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is semiconductor device that includes (1) a shallow trench isolation (STI) oxide region; (2) a first metal-oxide-semiconductor field-effect transistor (MOSFET) coupled to a first side of the STI oxide region; (3) a second MOSFET coupled to a second side of the STI oxide region, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (4) a dopant-implanted region below the STI oxide region, wherein the dopant-implanted region forms a portion of the BJT loop and is adapted to reduce a gain of the loop. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是包括（1）浅沟槽隔离（STI）氧化物区域的半导体器件; （2）耦合到所述STI氧化物区域的第一侧的第一金属氧化物半导体场效应晶体管（MOSFET）; （3）耦合到所述STI氧化物区域的第二侧的第二MOSFET，其中所述第一和第二MOSFET的部分形成耦合到环路中的第一和第二双极结型晶体管（BJT）; 和（4）STI氧化物区域下面的掺杂剂注入区域，其中掺杂剂注入区域形成BJT环路的一部分并且适于减小环路的增益。 提供了许多其他方面。