公开(公告)号：US5373254A

公开(公告)日：1994-12-13

申请号：US5034

申请日：1993-01-15

申请人： Toshihiko Nakauchi ,  Masato Hirai ,  Masami Kurata

发明人： Toshihiko Nakauchi ,  Masato Hirai ,  Masami Kurata

IPC分类号： H03L7/00 ,  G06F1/04 ,  H03K5/00 ,  H03L7/08 ,  H03L7/14 ,  H04L7/033 ,  H03L7/06

CPC分类号： H03L7/143

摘要： A method and apparatus for controlling the phase of a system clock, in which one of a first clock signal and a second clock signal is selected and output to a system as a system clock signal, the first clock signal being generated by a frequency synthesizer synchronized with an external clock signal supplied from a reference clock signal oscillator provided externally of the system, and the second clock signal being supplied from another reference clock signal oscillator provided internally of the system, and the phases of the first and second clock signals are controlled, prior to switching between the first and second clock signals and supplying the switched clock signal to the system as the system clock signal. The switching is delayed for a period while there is a phase shift between the first and second clock signal , when the system clock signal is switched between the first and second clock signal.

摘要翻译： 一种用于控制系统时钟的相位的方法和装置，其中选择第一时钟信号和第二时钟信号中的一个作为系统时钟信号输出到系统，第一时钟信号由频率合成器产生同步 具有从在系统外部提供的参考时钟信号振荡器提供的外部时钟信号，并且第二时钟信号由设置在系统内部的另一参考时钟信号振荡器提供，第一和第二时钟信号的相位被控制， 在第一和第二时钟信号之间切换并将切换的时钟信号提供给系统作为系统时钟信号。 当系统时钟信号在第一和第二时钟信号之间切换时，在第一和第二时钟信号之间存在相移时，开关被延迟一段时间。

公开(公告)号：US5455840A

公开(公告)日：1995-10-03

申请号：US123358

申请日：1993-09-17

申请人： Toshihiko Nakauchi ,  Masato Hirai

发明人： Toshihiko Nakauchi ,  Masato Hirai

IPC分类号： G06F1/12 ,  G06F1/04 ,  G06F1/10 ,  H03K5/1252 ,  H03K5/19 ,  H03L7/08 ,  H03L7/14 ,  H04L7/00 ,  H03K5/13

CPC分类号： G06F1/10 ,  H03K5/1252 ,  H03K5/19 ,  H03L7/08 ,  H03L7/0807 ,  H03L7/143 ,  H04L7/0083

摘要： A method of compensating a phase of a system clock for use in a system clock circuit for receiving an external clock to produce a system clock for an information processing system, in which the quantity of phase variation of the external clock supplied from a reference clock oscillator provided outside the system is detected; in accordance with the detected quantity of phase variation, the phase variation of the external clock supplied from the reference clock generator is compensated to supply the compensated external clock to the system clock circuit; whether or not a state of the external clock supplied from the reference clock oscillator provided outside the system is abnormal is detected; and in accordance with the detected state of the external clock, one of the external clock supplied from the reference clock oscillator and the compensated external clock is selected to supply the selected external clock to the system clock.

摘要翻译： 一种补偿系统时钟的相位的方法，用于在系统时钟电路中用于接收外部时钟以产生用于信息处理系统的系统时钟，其中从参考时钟振荡器提供的外部时钟的相位变化量 检测到系统外部; 根据检测到的相位变化量，从参考时钟发生器提供的外部时钟的相位变化被补偿以将经补偿的外部时钟提供给系统时钟电路; 检测从系统外部的参考时钟振荡器提供的外部时钟的状态是否异常; 并且根据检测到的外部时钟的状态，选择从参考时钟振荡器提供的外部时钟和经补偿的外部时钟之一来将所选择的外部时钟提供给系统时钟。

公开(公告)号：US5297292A

公开(公告)日：1994-03-22

申请号：US698956

申请日：1991-05-13

申请人： Shigeki Morimoto ,  Norikazu Endo ,  Toshihiko Nakauchi

发明人： Shigeki Morimoto ,  Norikazu Endo ,  Toshihiko Nakauchi

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F15/17 ,  G06F15/16

CPC分类号： G06F13/36 ,  G06F13/3625 ,  G06F15/17

摘要： A method is provided for controlling bus-using rights in a multi-bus system which has a plurality of buses and a plurality of units connected to each of the buses. A unit connected to one bus is accessible by another unit connected to another bus. When a first unit accesses either a second unit on the one bus or a third unit on another bus, two requests for use of the one and another buses are issued substantially at the same time, thereby reducing the time taken for acquiring a bus-using right of the another bus. As soon as it is found that access is directed to the second unit on the one bus, the request for using the another bus is canceled, thus reducing a bus occupation rate for the another bus.

摘要翻译： 提供一种用于在多总线系统中控制总线使用权限的方法，该多总线系统具有连接到每个总线的多个总线和多个单元。 连接到一个总线的单元可以通过连接到另一个总线的另一个单元访问。 当第一单元访问一个总线上的第二单元或另一个总线上的第三单元时，基本上同时发出两个使用一个和另一个总线的请求，从而减少获取总线使用所花费的时间 另一辆公共汽车的权利。 一旦发现接入被定向到一条总线上的第二单元，则取消使用另一总线的请求，从而降低了另一总线的总线占用率。