公开(公告)号：US07793183B2

公开(公告)日：2010-09-07

申请号：US11916702

申请日：2006-06-08

申请人： Toshihiko Yokota ,  Ken Namura ,  Mitsuru Sugimoto

发明人： Toshihiko Yokota ,  Ken Namura ,  Mitsuru Sugimoto

IPC分类号： G01R31/28

CPC分类号： G01R31/2812 ,  G01R31/2815 ,  G01R31/31855

摘要： Embodiments of the present invention provide a microcomputer on which a plurality of ICs (Integrated Circuits) connected from one another by a source-synchronous interface is mounted. The microcomputer includes an IC on the side for transmitting data through the source-synchronous interface which further includes: a PLL (Phase-Locked Loop) circuit being adapted for transmitting an operation clock in actual operation; a first flip-flop being adapted for transmitting test data in accordance with the operation clock transmitted from the PLL circuit; and a second flip-flop being adapted for transmitting a synchronous clock in source-synchronous, in accordance with the operation clock transmitted from the PLL circuit, a synchronous clock in source synchronous, and an IC on the side for receiving data through the source-synchronous interface which further includes a third flip-flop being adapted for capturing, in accordance with the synchronous clock transmitted from the second flip-flop, the test data transmitted from the first flip-flop. Methods for testing the microcomputer are also provided.

摘要翻译： 本发明的实施例提供了一种微型计算机，其上安装有通过源同步接口彼此连接的多个IC（集成电路）。 微型计算机包括：一侧的IC，用于通过源同步接口发送数据，该IC进一步包括：PLL（锁相环）电路，适于在实际操作中发送操作时钟; 第一触发器适于根据从PLL电路发送的操作时钟发送测试数据; 以及第二触发器，其适于根据从PLL电路发送的操作时钟，源同步的同步时钟和用于通过源极同步的接收数据的一侧的IC发送源同步的同步时钟， 同步接口还包括第三触发器，其适于根据从第二触发器发送的同步时钟从第一触发器发送的测试数据进行捕获。 还提供了测试微型计算机的方法。

公开(公告)号：US20090119561A1

公开(公告)日：2009-05-07

申请号：US11916702

申请日：2006-06-08

申请人： Toshihiko Yokota ,  Ken Namura ,  Mitsuru Sugimoto

发明人： Toshihiko Yokota ,  Ken Namura ,  Mitsuru Sugimoto

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/2812 ,  G01R31/2815 ,  G01R31/31855

摘要： Embodiments of the present invention provide a microcomputer on which a plurality of ICs (Integrated Circuits) connected from one another by a source-synchronous interface is mounted. The microcomputer includes an IC on the side for transmitting data through the source-synchronous interface which further includes: a PLL (Phase-Locked Loop) circuit being adapted for transmitting an operation clock in actual operation; a first flip-flop being adapted for transmitting test data in accordance with the operation clock transmitted from the PLL circuit; and a second flip-flop being adapted for transmitting a synchronous clock in source-synchronous, in accordance with the operation clock transmitted from the PLL circuit, a synchronous clock in source synchronous, and an IC on the side for receiving data through the source-synchronous interface which further includes a third flip-flop being adapted for capturing, in accordance with the synchronous clock transmitted from the second flip-flop, the test data transmitted from the first flip-flop. Methods for testing the microcomputer are also provided.

摘要翻译： 本发明的实施例提供了一种微型计算机，其上安装有通过源同步接口彼此连接的多个IC（集成电路）。 微型计算机包括：一侧的IC，用于通过源同步接口发送数据，该IC进一步包括：PLL（锁相环）电路，适于在实际操作中发送操作时钟; 第一触发器适于根据从PLL电路发送的操作时钟发送测试数据; 以及第二触发器，其适于根据从PLL电路发送的操作时钟，源同步的同步时钟和用于通过源极同步的接收数据的一侧的IC发送源同步的同步时钟， 同步接口还包括第三触发器，其适于根据从第二触发器发送的同步时钟从第一触发器发送的测试数据进行捕获。 还提供了测试微型计算机的方法。

公开(公告)号：US20070198882A1

公开(公告)日：2007-08-23

申请号：US11672072

申请日：2007-02-07

申请人： Ken Namura ,  Sanae Seike ,  Toshihiko Yokota

发明人： Ken Namura ,  Sanae Seike ,  Toshihiko Yokota

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31726 ,  G01R31/318594

摘要： A method and integrated circuit for LSSD testing. The integrated circuit includes a plurality of clock domains supplied with test clocks from separate clock generation circuits. In each clock domain, a scan latch at a clock domain boundary receiving an input from another clock domain includes a master latch for latching an input in response to a first clock, a slave latch for latching an output from the master latch in response to a second clock, a selector for supplying the master latch with a system input when the mode selection signal is at a second level, and a clock control circuit for turning off the first clock when the mode selection signal transits from the first level to the second level.

摘要翻译： 一种用于LSSD测试的方法和集成电路。 集成电路包括从单独的时钟发生电路提供有测试时钟的多个时钟域。 在每个时钟域中，在接收来自另一时钟域的输入的时钟域边界处的扫描锁存器包括用于响应于第一时钟锁存输入的主锁存器，用于响应于主器件锁存来自主锁存器的输出的从锁存器 第二时钟，当模式选择信号处于第二电平时，用于向主锁存器提供系统输入的选择器;以及当模式选择信号从第一电平转换到第二电平时关闭第一时钟的时钟控制电路 。

公开(公告)号：US07752513B2

公开(公告)日：2010-07-06

申请号：US11672072

申请日：2007-02-07

申请人： Ken Namura ,  Sanae Seike ,  Toshihiko Yokota

发明人： Ken Namura ,  Sanae Seike ,  Toshihiko Yokota

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31726 ,  G01R31/318594

摘要： A method and integrated circuit for LSSD testing. The integrated circuit includes a plurality of clock domains supplied with test clocks from separate clock generation circuits. In each clock domain, a scan latch at a clock domain boundary receiving an input from another clock domain includes a master latch for latching an input in response to a first clock, a slave latch for latching an output from the master latch in response to a second clock, a selector for supplying the master latch with a system input when the mode selection signal is at a second level, and a clock control circuit for turning off the first clock when the mode selection signal transits from the first level to the second level.

摘要翻译： 一种用于LSSD测试的方法和集成电路。 集成电路包括从单独的时钟发生电路提供有测试时钟的多个时钟域。 在每个时钟域中，在接收来自另一时钟域的输入的时钟域边界处的扫描锁存器包括用于响应于第一时钟锁存输入的主锁存器，用于响应于主器件锁存来自主锁存器的输出的从锁存器 第二时钟，当模式选择信号处于第二电平时，用于向主锁存器提供系统输入的选择器;以及当模式选择信号从第一电平转换到第二电平时关闭第一时钟的时钟控制电路 。

公开(公告)号：US06813706B2

公开(公告)日：2004-11-02

申请号：US09838012

申请日：2001-04-19

申请人： Nobuyoshi Tanaka ,  Ken Namura

发明人： Nobuyoshi Tanaka ,  Ken Namura

IPC分类号： G06F938

CPC分类号： G06F5/10 ,  G06F2205/064

摘要： The present invention provides an information processing system that can have the optimum number of FIFO stages dynamically at any given time so that the system makes it possible to omit analyzing of the number of FIFO stages from data characteristics so as to improve the performance. The information processing system includes a data FIFO 22 for storing data sets and a next pointer 29 having the same number of storage positions as that of the data FIFO 22. A preceding data set is stored in the storage position “1” of the data FIFO 22 and a subsequent data set is stored in the storage position “7” of the data FIFO 22. At this time, the storage position “1” of the next pointer 29 stores “7” as information on a storage position for the subsequent data set. According to this information “7”, the subsequent data set is read from the storage position “7” of the data FIFO 22.

摘要翻译： 本发明提供了一种信息处理系统，其可以在任何给定时间动态地具有最佳数量的FIFO级，使得系统能够从数据特征中省略对FIFO级数的分析，从而提高性能。 信息处理系统包括用于存储数据集的数据FIFO 22和具有与数据FIFO22相同数量的存储位置的下一个指针29.先前的数据集存储在数据FIFO的存储位置“1” 22，随后的数据集存储在数据FIFO22的存储位置“7”中。此时，下一个指针29的存储位置“1”存储“7”作为关于后续数据的存储位置的信息 组。 根据该信息“7”，从数据FIFO22的存储位置“7”读取后续的数据组。

公开(公告)号：US06988120B2

公开(公告)日：2006-01-17

申请号：US10162812

申请日：2002-06-04

申请人： Yoshinao Kobayashi ,  Ken Namura ,  Kenya Katoh

发明人： Yoshinao Kobayashi ,  Ken Namura ,  Kenya Katoh

IPC分类号： G06F7/552

CPC分类号： G06F7/552 ,  G06F7/483

摘要： A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable to perform a look ahead operation and establish the location of the MSB (Most Significant Bit) in the calculation results; and combinational circuits for performing the rounding off process and the calculation of the variables by using information concerning a carry, which is generated by the pseudo carry generator and based on the location of the MSB determined by the MSB look ahead circuit.