公开(公告)号：US20120261735A1

公开(公告)日：2012-10-18

申请号：US13538638

申请日：2012-06-29

申请人： Toshihiro IIZUKA ,  Tomoe YAMAMOTO ,  Mami TODA ,  Shintaro YAMAMICHI

发明人： Toshihiro IIZUKA ,  Tomoe YAMAMOTO ,  Mami TODA ,  Shintaro YAMAMICHI

IPC分类号： H01L27/108

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO.sub.2, HfO.sub.2, (Zr.sub.x, Hf.sub.1−x)O.sub.2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr.sub.x，Hf x-x）O 2中的至少一种材料形成 0

公开(公告)号：US20080048228A1

公开(公告)日：2008-02-28

申请号：US11834090

申请日：2007-08-06

申请人： Takashi SAKOH ,  Mami TODA

发明人： Takashi SAKOH ,  Mami TODA

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L23/585 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening.A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26 and 28 are formed on a semiconductor substrate 10. The seal ring 30 is formed in the interlayer insulating films 22, 24, 26 and 28, and at least a portion there of is located spaced apart from the semiconductor substrate 10.

摘要翻译： 在传统的半导体器件中，在形成接触插塞的开口的部分中发生过度的蚀刻，对位于开口下方的扩散层造成损坏。 半导体器件1包括用于形成电路的区域D 1和围绕用于形成电路的区域D 1的密封环30（保护环）。 在用于形成电路的区域D 1中形成DRAM 40。 层间绝缘膜22,24,26和28形成在半导体衬底10上。 密封环30形成在层间绝缘膜22,24,26和28中，并且其中的至少一部分与半导体衬底10间隔开。

公开(公告)号：US20080197392A1

公开(公告)日：2008-08-21

申请号：US12031937

申请日：2008-02-15

申请人： Takashi SAKOH ,  Mami TODA

发明人： Takashi SAKOH ,  Mami TODA

IPC分类号： H01L27/108

CPC分类号： H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： A semiconductor memory device has bit lines, capacitors, bit contacts and capacitor contacts, wherein the bit lines are provided over a semiconductor substrate, the bit lines are connected to the semiconductor substrate through the bit contacts, the capacitors are connected to the semiconductor substrate through the capacitor contacts, and wherein in two adjacent bit lines, pitch d2 (first pitch) representing a pitch of portions provided with the capacitor contacts is larger than pitch d3 (second pitch) representing a pitch of portions provided with the bit contacts, and distance d4 between two such bit lines in the portions provided with the bit contacts is larger than width d5 of the bit lines in the portions provided with the bit contacts.

摘要翻译： 半导体存储器件具有位线，电容器，位触点和电容器触点，其中位线设置在半导体衬底上，位线通过位触点连接到半导体衬底，电容器通过 电容器触点，并且其中在两个相邻位线中，表示设置有电容器触点的部分的间距的间距d 2（第一间距）大于表示设置有位触点的部分的间距的间距d 3（第二间距） 并且设置有位触点的部分中的两个这样的位线之间的距离d 4大于设置有位触点的部分中的位线的宽度d 5。