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22 条记录 (耗时 0.028 秒)

    Gate array device having a memory cell/interconnection region
    1.
    发明授权
    Gate array device having a memory cell/interconnection region 失效
    具有存储单元/互连区域的门阵列器件

    公开(公告)号：US4922441A

    公开(公告)日：1990-05-01

    申请号：US143715

    申请日：1988-01-14

    申请人： Toshihiro Tsukagoshi ,  Masanobu Fukushima ,  Keiichi Yoshioka ,  Takashi Yasui

    发明人： Toshihiro Tsukagoshi ,  Masanobu Fukushima ,  Keiichi Yoshioka ,  Takashi Yasui

    IPC分类号： G11C11/412 ,  G11C17/12 ,  H01L27/11 ,  H01L27/118 ,  H03K19/173 ,  G06F15/60

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C17/12 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/118 ,  H03K19/1735

    摘要： A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.

    摘要翻译： 门阵列器件包括彼此间隔开的多个基本单元区域，从而在其间限定多个中间区域。 每个中间区域可以至少部分地用作存储器或功能单元区域或者作为互连区域。 可以通过金属化将存储单元区域选择性地定义为ROM或RAM。 可以根据控制信号选择性地设置测试模式或正常操作模式。 当正常操作模式被设置时，输入端通过逻辑电路可操作地连接到存储器电路; 而当设置测试模式时，输入端直接连接到存储器电路，同时旁路逻辑电路。 还提供了一种存储单元结构，其可以被定义为RAM存储器单元或者通过金属化存储选择的二进制数据的ROM存储单元。

    HEAD DRIVING DEVICE AND IMAGE FORMING APPARATUS INCLUDING SAME
    2.
    发明申请
    HEAD DRIVING DEVICE AND IMAGE FORMING APPARATUS INCLUDING SAME 有权

    公开(公告)号：US20210060937A1

    公开(公告)日：2021-03-04

    申请号：US16999425

    申请日：2020-08-21

    申请人： Tomohiro Mizutani ,  Katsuhiro Tobita ,  Toshihiro Tsukagoshi ,  Takatsugu Maeda

    发明人： Tomohiro Mizutani ,  Katsuhiro Tobita ,  Toshihiro Tsukagoshi ,  Takatsugu Maeda

    IPC分类号： B41J2/045

    摘要： There is provided a head driving device for causing a head to discharge droplets. The device includes a drive circuit, a first drive waveform generation circuit, a second drive waveform generation circuit, and a correction circuit. The drive circuit is configured to drive the head based on a plurality of drive waveforms to discharge the droplets. The first drive waveform generation circuit configured to generate a first drive waveform of the plurality of drive waveforms. The second drive waveform generation circuit is configured to generate a second drive waveform of the plurality of drive waveforms. The correction circuit is configured to correct the first drive waveform and the second drive waveform with reference to an intermediate potential.

    Neuron unit, neural network and signal processing method
    5.
    发明授权
    Neuron unit, neural network and signal processing method 失效
    神经元，神经网络和信号处理方法

    公开(公告)号：US5167006A

    公开(公告)日：1992-11-24

    申请号：US629632

    申请日：1990-12-18

    申请人： Toshiyuki Furuta ,  Hiroyuki Horiguchi ,  Hirotoshi Eguchi ,  Yutaka Ebi ,  Tatsuya Furukawa ,  Yoshio Watanabe ,  Toshihiro Tsukagoshi

    发明人： Toshiyuki Furuta ,  Hiroyuki Horiguchi ,  Hirotoshi Eguchi ,  Yutaka Ebi ,  Tatsuya Furukawa ,  Yoshio Watanabe ,  Toshihiro Tsukagoshi

    IPC分类号： G06N3/063

    CPC分类号： G06N3/063

    摘要： A neuron unit processes a plurality of input signals and outputs an output signal which is indicative of a result of the processing. The neuron unit includes input lines for receiving the input signals, a forward process part including a supplying part for supplying weight functions and an operation part for carrying out an operation on each of the input signals using one of the weight functions and for outputting the output signal, and a self-learning part including a generating part for generating new weight functions based on errors between the output signal of the forward process part and teaching signals and a varying part for varying the weight functions supplied by the supplying part of the forward process part to the new weight functions generated by the generating part.

    摘要翻译： 神经元单元处理多个输入信号并输出​​指示处理结果的输出信号。 神经元单元包括用于接收输入信号的输入线，包括用于提供加权函数的供给部分的前向处理部分和使用加权函数之一对每个输入信号执行操作的操作部分，并且用于输出输出 信号和自学习部分，其包括基于正向处理部分的输出信号和示教信号之间的误差产生新的加权函数的生成部分和用于改变由前向处理的供给部分提供的加权函数的变化部分 部分由生成部分生成的新的权重函数。

    LIQUID DISCHARGE CONTROL DEVICE AND LIQUID DISCHARGE APPARATUS INCORPORATING SAME
    6.
    发明申请
    LIQUID DISCHARGE CONTROL DEVICE AND LIQUID DISCHARGE APPARATUS INCORPORATING SAME 有权

    公开(公告)号：US20210339525A1

    公开(公告)日：2021-11-04

    申请号：US17223193

    申请日：2021-04-06

    申请人： Toshihiro Tsukagoshi

    发明人： Toshihiro Tsukagoshi

    IPC分类号： B41J2/045

    摘要： A liquid discharge control device includes an adhesion state detector and circuitry. The adhesion state detector detects an adhesion state of a droplet adhering to a medium being conveyed. The droplet is discharged from a liquid discharge device. The circuitry controls a discharge operation of the liquid discharge device based on an operation parameter, determines a difference between the adhesion state of the droplet and a reference adhesion state of the droplet on the medium being conveyed, and updates the operation parameter based on a determination result.

    Neuron unit
    9.
    发明授权
    Neuron unit 失效
    神经元单位

    公开(公告)号：US5327522A

    公开(公告)日：1994-07-05

    申请号：US989781

    申请日：1992-12-11

    申请人： Toshiyuki Furuta ,  Hiroyuki Horiguchi ,  Hirotoshi Eguchi ,  Yutaka Ebi ,  Tatsuya Furukawa ,  Yoshio Watanabe ,  Toshihiro Tsukagoshi ,  Takahiro Watanabe ,  Shuji Motomura ,  Atsuo Hashimoto ,  Sugitaka Oteki ,  Satoshi Otsuki ,  Eiki Aono ,  Takashi Kitaguchi

    发明人： Toshiyuki Furuta ,  Hiroyuki Horiguchi ,  Hirotoshi Eguchi ,  Yutaka Ebi ,  Tatsuya Furukawa ,  Yoshio Watanabe ,  Toshihiro Tsukagoshi ,  Takahiro Watanabe ,  Shuji Motomura ,  Atsuo Hashimoto ,  Sugitaka Oteki ,  Satoshi Otsuki ,  Eiki Aono ,  Takashi Kitaguchi

    IPC分类号： G06N3/063 ,  G06F15/18

    CPC分类号： G06N3/063

    摘要： A neuron unit processes a plurality of input signals and for outputs an output signal which is indicative of a result of the processing, and includes input lines for receiving the input signals, a forward process part including a supplying part for supplying weight functions and an operation part for carrying out an operation on each of the input signals using one of the weight functions and for outputting the output signal, and a self-learning part including a function generating part for generating new weight functions based on errors between the output signal of the forward process part and teaching signals and a varying part for varying the weight functions supplied by the supplying part of the forward process part to the new weight functions generated by the generating part. The supplying part includes a memory for storing each weight function in the form of a binary value, and a generating circuit for generating a random pulse train based on each binary value stored in the memory. The random pulse train describes each weight function in the form of a pulse signal having a pulse density.

    摘要翻译： 神经元单元处理多个输入信号并输出​​表示处理结果的输出信号，并且包括用于接收输入信号的输入线，前向处理部分，包括用于提供加权函数的提供部分和操作 使用所述加权函数之一对所述输入信号执行操作并输出所述输出信号的部分，以及包括功能生成部分的自学习部分，用于基于所述输入信号的输出信号之间的误差生成新的加权函数 前向处理部分和教学信号，以及变化部分，用于将由前向处理部分的供给部分提供的权重函数改变为由生成部分生成的新的权重函数。 供给部分包括用于以二进制值的形式存储每个加权函数的存储器，以及用于基于存储在存储器中的每个二进制值产生随机脉冲串的产生电路。 随机脉冲串以具有脉冲密度的脉冲信号的形式描述每个权重函数。

    Knowledge inferential processing apparatus
    10.
    发明授权
    Knowledge inferential processing apparatus 失效
    知识推理处理设备

    公开(公告)号：US5051923A

    公开(公告)日：1991-09-24

    申请号：US388564

    申请日：1989-08-01

    申请人： Toshihiro Tsukagoshi

    发明人： Toshihiro Tsukagoshi

    IPC分类号： G06F9/44 ,  G06F17/30 ,  G06N5/00 ,  G06N5/04

    CPC分类号： G06N5/003 ,  G06N5/04

    摘要： A knowledge inferential processing apparatus comprises an external interface section for inputting and outputting information between the knowledge inferential processing apparatus and the exterior thereof; a rule base memory for representing knowledge as a combination of a plurality of rules constructing a premise conditional section and a conclusive section as a pair, and storing the represented knowledge; a rule pointer table for storing a rule pointer group indicative of a sequence for applying the rules within the rule base memory; an inferential processing section for interpreting and executing the rules and judging whether or not the matching is formed with respect to the respective rules; a memory section for storing fact data sent to the inferential processing section and conclusive data generated during the inferential processing; an inferential hysteresis recording section for recording a rule pointer of the matched rule in the matched sequence with respect to the inferential processing results executed by the inferential processing section; and a control section for sequentially sending the rules to the inferential processing section in accordance with the rule pointer group and sending the rule pointer of the matched rule to the inferential hysteresis recording section with respect to the inferential processing results executed by the inferential processing section.

    摘要翻译： 知识推理处理装置包括用于在知识推理处理装置和其外部之间输入和输出信息的外部接口部分; 用于将构成前提条件部分和结论部分的多个规则的组合的知识表示为一对的规则库存储器，并且存储所表示的知识; 规则指针表，用于存储指示用于在规则库内规则中应用规则的序列的规则指针组; 推理处理部分，用于解释和执行规则，并判断相关规则是否形成匹配; 用于存储发送到推理处理部分的事实数据的存储部分和在推理处理期间产生的确定数据; 推定滞后记录部分，用于相对于推理处理部分执行的推理处理结果，记录匹配规则的规则指针; 以及控制部分，用于根据规则指针组顺序地将规则发送到推理处理部分，并将匹配规则的规则指针相对于由推理处理部分执行的推理处理结果发送到推导迟滞记录部分。