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    Semiconductor integrated circuit device with high and low voltage wells
    6.
    发明授权
    Semiconductor integrated circuit device with high and low voltage wells 失效
    具有高低压井的半导体集成电路器件

    公开(公告)号：US06495896B1

    公开(公告)日：2002-12-17

    申请号：US09407401

    申请日：1999-09-28

    申请人： Toshitake Yaegashi ,  Seiichi Aritome ,  Yuji Takeuchi ,  Kazuhiro Shimizu

    发明人： Toshitake Yaegashi ,  Seiichi Aritome ,  Yuji Takeuchi ,  Kazuhiro Shimizu

    IPC分类号： H01L2900

    CPC分类号： H01L27/11526 ,  H01L21/761 ,  H01L21/823878 ,  H01L27/11531

    摘要： A semiconductor integrated circuit device comprises an n-type well 8-1 formed in a p-type silicon substrate 1, an n-type well 8-2 formed so as to surround a part of the substrate 1, in which a p−-type well is formed, a p−-type well 15-1 formed in the substrate 1, a p−-type well 15-2 formed in a part of the substrate 1, which is surrounded by the n-type well, an embedded n-type well 12-1 formed below the p−-type well 15-1, and an n-type well 12-2 which is formed below the p−-type well 15-2 and which is connected to the n-type well 8-2. Thus, it is possible to provide a semiconductor integrated circuit device capable of suppressing the increase of the number of photolithography steps and reducing the manufacturing costs. Alternatively, low-voltage n-channel MOS transistors QN1, QN2 and low-voltage p-channel MOS transistors QP1, QP2 are formed in a p-type well 214 and n-type well 213 of a p−-type silicon substrate 211, respectively, and high-voltage n-channel MOS transistors QN3, QN4 are formed in the substrate 211. The p-type well 214, in which the transistors QN1, QN2 are formed, and the p-type element isolating layer 215 of the element isolating regions for the transistors QN3, QN4 are simultaneously formed by ion implantation using a resist mask by the lithography on a flat surface having no step. The p-type well 214 and the p-type element isolating layer 215 have the same depth from the substrate surface of the element regions and the same impurity density. Thus, it is possible to provide a semiconductor integrated circuit device capable of achieving good element isolation characteristics, and a method for producing the same.

    摘要翻译： 半导体集成电路器件包括形成在p型硅衬底1中的n型阱8-1，形成为围绕衬底1的一部分的n型阱8-2，其中p型 形成良好的p型阱15-1，形成在衬底1中的p型阱15-1，形成在衬底1的被n型阱包围的部分中的p型阱15-2，嵌入 n型阱12-1形成在p型阱15-1的下方，n型阱12-2形成在p型阱15-2的下方，并与n型阱15-1连接。 好8-2。 因此，可以提供能够抑制光刻步骤数量增加并降低制造成本的半导体集成电路器件。或者，低电压n沟道MOS晶体管QN1，QN2和低压p沟道MOS 晶体管QP1，QP2分别形成在p型硅衬底211的p型阱214和n型阱213中，并且高压n沟道MOS晶体管QN3，QN4形成在衬底211中。 其中形成晶体管QN1，QN2的p型阱214和用于晶体管QN3，QN4的元件隔离区的p型元件隔离层215同时通过使用光刻胶的抗蚀剂掩模的离子注入形成 在没有台阶的平坦表面上。 p型阱214和p型元件隔离层215具有与元件区域的衬底表面相同的深度和相同的杂质密度。 因此，可以提供能够实现良好元件隔离特性的半导体集成电路器件及其制造方法。