公开(公告)号：US06444549B2

公开(公告)日：2002-09-03

申请号：US09144938

申请日：1998-09-01

申请人： Toshiya Hayashi ,  Kouji Hamada ,  Naoharu Nishio ,  Kousuke Miyoshi ,  Shuichi Saito

发明人： Toshiya Hayashi ,  Kouji Hamada ,  Naoharu Nishio ,  Kousuke Miyoshi ,  Shuichi Saito

IPC分类号： H01L21425

CPC分类号： H01L29/6609 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/324

摘要： Upon fabrication of semiconductor devices, a semiconductor substrate is subjected to ion implantation with high energy. Subsequent annealing of the ion-implanted semiconductor substrate, when conducted by heating the substrate to a temperature of from 1,000° C. to 1,200° C. at a ramp-up rate of at least 200° C./sec, makes it possible to provide the resulting semiconductor devices with smaller leakage currents of reduced variations (&sgr;/X). The present invention can therefore provide a process for the fabrication of semiconductor devices featuring both smaller leakage currents and reduced variations of the leakage currents even when ion implantation is conducted with high energy.

摘要翻译： 在制造半导体器件时，以高能量对半导体衬底进行离子注入。 离子注入的半导体衬底的随后的退火，当通过以至少200℃/秒的升温速度将衬底加热至1000℃至1200℃的温度进行时，可以使 为所得到的半导体器件提供具有减小的变化（sigma / X）的较小泄漏电流。 因此，本发明可以提供制造半导体器件的方法，即使当以高能量进行离子注入时，具有更小的漏电流和漏电流的减小的变化。

公开(公告)号：US06479369B1

公开(公告)日：2002-11-12

申请号：US09705782

申请日：2000-11-06

申请人： Kousuke Miyoshi

发明人： Kousuke Miyoshi

IPC分类号： H01L2176

CPC分类号： H01L21/31055 ,  H01L21/76224

摘要： A method of forming a shallow trench isolation, includes the steps, in sequence, of (a) forming a mask pattern on a silicon substrate, the mask pattern being made of a silicon dioxide layer and a silicon nitride layer, (b) forming a trench in the silicon substrate with the mask pattern being used as a mask, (c) forming a first silicon dioxide film covering an inner surface of the trench such that the trench is not filled with the first silicon dioxide film, (d) heating the first silicon dioxide film, (e) forming a second silicon dioxide film over a product resulted from the step (d) such that the trench is filled with the second silicon dioxide film, (f) heating the second silicon dioxide film, (g) polishing the first and second silicon dioxide films through the use of the silicon nitride layer as a stopper, (h) etching the silicon nitride layer for removal, and (i) etching the first and second silicon dioxide films such that the first and second silicon dioxide films are on a level with a surface of the silicon substrate.

摘要翻译： 形成浅沟槽隔离的方法包括以下步骤：（a）在硅衬底上形成掩模图案，掩模图案由二氧化硅层和氮化硅层制成，（b）形成 将掩模图案用作掩模的硅衬底中的沟槽，（c）形成覆盖沟槽的内表面的第一二氧化硅膜，使得沟槽未被第一二氧化硅膜填充，（d）加热 （e）从步骤（d）产生的产品上形成第二二氧化硅膜，使得沟槽填充有第二二氧化硅膜，（f）加热第二二氧化硅膜，（g） 通过使用氮化硅层作为阻挡层来研磨第一和第二二氧化硅膜;（h）蚀刻氮化硅层以进行去除，以及（i）蚀刻第一和第二二氧化硅膜，使得第一和第二硅 二氧化碳电影是一个水平的wi 在硅衬底的表面上。

公开(公告)号：US5801101A

公开(公告)日：1998-09-01

申请号：US689248

申请日：1996-08-07

申请人： Kousuke Miyoshi

发明人： Kousuke Miyoshi

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/52 ,  H01L21/306

CPC分类号： H01L21/3213

摘要： Disclosed herein is, a method of forming a metal wiring on a semiconductor substrate dry etching a metal wiring film or a laminated structure film comprising a metal wiring film and a metal barrier film, which includes a first step of performing etching to a metal wiring film and a second dry etching step of overetching the metal wiring film or the metal barrier film under such a condition that the residence time of a gas in an etching chamber in the second dry etching step is shorter than a residence time of a gas in the first etching step.

摘要翻译： 本发明公开了一种在半导体衬底上形成金属布线的方法，干蚀刻金属布线膜或包括金属布线膜和金属阻挡膜的层压结构膜，其包括对金属布线膜进行蚀刻的第一步骤 以及在第二干法蚀刻工序中的蚀刻室内的气体停留时间短于第一干法蚀刻工序中的气体停留时间的条件下，对金属布线膜或金属阻挡膜进行过蚀刻的第二干式蚀刻工序 蚀刻步骤。

公开(公告)号：US5660673A

公开(公告)日：1997-08-26

申请号：US475450

申请日：1994-08-17

申请人： Kousuke Miyoshi

发明人： Kousuke Miyoshi

IPC分类号： C23F4/00 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065 ,  H05H1/00

CPC分类号： H01J37/32642 ,  Y10S156/915

摘要： An apparatus for dry etching includes a vacuum chamber into which an etching gas is to be introduced, an electrode disposed in the vacuum chamber, a material to be etched being placed on an upper surface of the electrode, at least one cylindrical ring disposed around the material, and a device for raising and lowering the rings so that the rings are raised above or lowered below the upper surface of the electrode.

摘要翻译： 一种用于干法蚀刻的设备包括：真空室，其中将引入蚀刻气体，设置在真空室中的电极，待蚀刻的材料放置在电极的上表面上;至少一个圆柱形环， 材料和用于升高和降低环的装置，使得环在电极的上表面上方或下方升高。

公开(公告)号：US06258635B1

公开(公告)日：2001-07-10

申请号：US09164970

申请日：1998-10-01

申请人： Kousuke Miyoshi ,  Seiichi Shishiguchi

发明人： Kousuke Miyoshi ,  Seiichi Shishiguchi

IPC分类号： H01L21335

CPC分类号： H01L21/28211 ,  H01L21/26513 ,  H01L21/28167 ,  H01L21/3221

摘要： A method of manufacturing a semiconductor device has a step whereby, when forming a gate oxide film, a thin oxide film is left on a silicon substrate onto which it is formed and whereby a heavy metal at the surface of the silicon substrate is diffused into the substrate, and a step of forming a gate oxide film onto the silicon substrate.

摘要翻译： 一种制造半导体器件的方法具有以下步骤：当形成栅极氧化膜时，在其所形成的硅衬底上留下薄的氧化膜，由此将硅衬底表面的重金属扩散到 衬底，以及在硅衬底上形成栅极氧化膜的步骤。