公开(公告)号：US20060186478A1

公开(公告)日：2006-08-24

申请号：US11067200

申请日：2005-02-24

Applicant: Peter Hughes ,  Shannon Morton ,  Trevor Monk

Inventor： Peter Hughes ,  Shannon Morton ,  Trevor Monk

IPC: H01L29/94

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.

Abstract translation: 公开了一种用于优化由标准单元（12）构建的半导体集成电路中的晶体管性能或定制晶体管级布局的方法（300）。 NMOS扩散的有源区域在两个相邻单元（112）之间的连接区域（102）延伸，在每个单元的相邻边缘处具有与扩散相同的网。 扩散区域扩展以限制有源和非活性界面的发生，以最小化晶格应变效应并提高晶体管性能。

公开(公告)号：US6150865A

公开(公告)日：2000-11-21

申请号：US350498

申请日：1999-07-09

Applicant: Steven Fluxman ,  Trevor Monk

Inventor： Steven Fluxman ,  Trevor Monk

IPC: G06F1/10 ,  G06F17/50 ,  H03K19/096

CPC classification number: G06F17/5077 ,  G06F1/10 ,  G06F2217/62

Abstract: A method for positioning/routing a clock circuit for an integrated circuit compensates for phase differences by adjusting secondary amplifiers having adjustable input delays. The method includes the steps of positioning first conductive lines parallel to a first direction evenly spaced with respect to the second direction. The first conductive lines are connected to outputs of the first amplifiers. A balanced tree-like structure provides each of the first amplifiers a clock signal coming from a single source. The method further includes the steps of positioning functional blocks for forming the integrated circuit, and the positioning of second lines parallel to the second direction. Each secondary amplifier is routed to the closest second line. An equivalent electrical diagram corresponding to the path taken by the clock signal between the input of the tree-like structure device and the input of each secondary amplifier is determined. The analog simulation of the equivalent electrical diagram and the measurement of the phase delays at the input of each secondary amplifier are performed. The input delay of each secondary amplifier is then adjusted to correspond to the largest measured phase delay.

Abstract translation: 用于定位/布线集成电路的时钟电路的方法通过调节具有可调输入延迟的次级放大器来补偿相位差。 该方法包括以下步骤：将第一导线平行于相对于第二方向均匀间隔开的第一方向。 第一导线连接到第一放大器的输出。 平衡的树状结构为每个第一放大器提供来自单个源的时钟信号。 该方法还包括以下步骤：定位用于形成集成电路的功能块以及平行于第二方向的第二线的定位。 每个辅助放大器被路由到最接近的第二行。 确定与树形结构装置的输入端和每个次级放大器的输入端之间的时钟信号所采取的路径对应的等效电路图。 执行等效电气图的模拟仿真和每个次级放大器的输入处的相位延迟的测量。 然后调整每个次级放大器的输入延迟以对应于最大测量的相位延迟。

公开(公告)号：US08076907B2

公开(公告)日：2011-12-13

申请号：US12222296

申请日：2008-08-06

Applicant: Masautso Sau Ngosi ,  Trevor Monk ,  Zoran Miletic

Inventor： Masautso Sau Ngosi ,  Trevor Monk ,  Zoran Miletic

IPC: H01M10/44 ,  H01M10/46

CPC classification number: H02J7/35 ,  H02J9/06 ,  Y02B10/72

Abstract: A method of charging a battery in a system involving a renewable energy source and operable to supply at least some electrical energy from the renewable energy source to a third party involves causing a charge controller operably connected to the renewable energy source to receive the electrical energy from the renewable energy source and operably connected to the battery, to charge the battery, using only the electrical energy from the renewable energy source, according to a charging sequence. The charging sequence includes at least a bulk charge period wherein the battery is charged at a relatively constant charging current, an absorption period following the bulk charge period wherein the battery is charged in an absorption mode, and a float period following the absorption period wherein the battery is charged in a float charging mode.

Abstract translation: 在涉及可再生能源的系统中对电池充电并且可操作以将可再生能源至少提供一些电能提供给第三方的方法包括使可操作地连接到可再生能源的充电控制器从电能接收来自第 可再生能源并且可操作地连接到电池，以根据充电顺序仅使用来自可再生能源的电能对电池充电。 充电序列至少包括大量充电期间，其中电池以相对恒定的充电电流充电，大容量充电周期之后的吸收周期，其中电池以吸收模式充电，以及吸收周期之后的浮动周期，其中 电池以浮充电模式充电。

公开(公告)号：US20100033124A1

公开(公告)日：2010-02-11

申请号：US12222296

申请日：2008-08-06

Applicant: Masautso Sau Ngosi ,  Trevor Monk ,  Zoran Miletic

Inventor： Masautso Sau Ngosi ,  Trevor Monk ,  Zoran Miletic

IPC: H02J7/00

CPC classification number: H02J7/35 ,  H02J9/06 ,  Y02B10/72

Abstract: A method of charging a battery in a system involving a renewable energy source and operable to supply at least some electrical energy from the renewable energy source to a third party involves causing a charge controller operably connected to the renewable energy source to receive the electrical energy from the renewable energy source and operably connected to the battery, to charge the battery, using only the electrical energy from the renewable energy source, according to a charging sequence. The charging sequence includes at least a bulk charge period wherein the battery is charged at a relatively constant charging current, an absorption period following the bulk charge period wherein the battery is charged in an absorption mode, and a float period following the absorption period wherein the battery is charged in a float charging mode.

Abstract translation: 在涉及可再生能源的系统中对电池充电并且可操作以将可再生能源至少提供一些电能提供给第三方的方法包括使可操作地连接到可再生能源的充电控制器从电能接收来自第 可再生能源并且可操作地连接到电池，以根据充电顺序仅使用来自可再生能源的电能对电池充电。 充电序列至少包括大量充电期间，其中电池以相对恒定的充电电流充电，大容量充电周期之后的吸收周期，其中电池以吸收模式充电，以及吸收周期之后的浮动周期，其中 电池以浮充电模式充电。

公开(公告)号：US06133796A

公开(公告)日：2000-10-17

申请号：US221296

申请日：1998-12-23

Applicant: Trevor Monk

Inventor： Trevor Monk

IPC: H03K23/54 ,  H03K23/66 ,  H03L7/16

CPC classification number: H03L7/183 ,  H03K23/544 ,  H03K23/66 ,  H03K23/667

Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages. The circuit includes a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and wherein the second plurality M of transistor stages includes at least some of said first plurality N of transistor stages, including said first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the circuit operates as a divide-by-M circuit in which an output signal is generated which has one cycle for every M cycles of a clock signal applied to the transistor stages. The circuit includes a switching circuit having at least two inputs and arranged to selectively connect to the first stage, the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Abstract translation: 可编程分频电路包括以N分频序列连接的第一多个N个相似的晶体管级，其中N为奇整数，晶体管级配置成使得当最后级的输出提供给第一级时 按照该顺序，分频电路作为N分频电路工作，其中产生一个输出信号，对于施加到晶体管级的时钟信号的每N个周期，产生一个周期。 该电路包括可选择地以M分频序列与第二多个晶体管级M连接的三态反相器，其中M为偶数整数，并且其中第二多个M晶体管级包括至少部分所述第一 多个N个晶体管级，包括所述第一级，由此当M分频序列中的最后级的输出被提供给第一级时，该电路作为除M电路工作，其中输出信号 被产生，其对于施加到晶体管级的时钟信号的每M个周期具有一个周期。 该电路包括具有至少两个输入并且被布置为选择性地连接到第一级的输入，N分频或M分频序列中的最后级的输出，由此该电路可以是 被编程为以N分频或M分频电路运行。

公开(公告)号：US06208179B1

公开(公告)日：2001-03-27

申请号：US09220978

申请日：1998-12-23

Applicant: Trevor Monk

Inventor： Trevor Monk

IPC: H03B1900

CPC classification number: H03L7/183 ,  H03K23/44 ,  H03K23/544 ,  H03K23/66

Abstract: A dividing circuit comprises a plurality (N) of transistor stages connected in a ring. Each stage comprises a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node, a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, wherein control nodes of a first transistor of each said transistor pair are connected together to provide an input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide a clock node for the stage, wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than a duty cycle of said clock signal.

Abstract translation: 分频电路包括以环形连接的多个（N）个晶体管级。 每个级包括串联连接在第一电压电平和输出节点之间的第一导电类型的第一对晶体管，第二导电类型的第二对晶体管串联连接在第二电压电平和所述输出节点之间，其中 每个所述晶体管对的第一晶体管的控制节点连接在一起以提供用于该级的输入节点，并且每个所述晶体管对的第二晶体管的控制节点连接在一起以为该级提供时钟节点，其中输入 每个级的节点连接到前级的输出节点，由此在每个所述输出节点处产生输出信号，输出信号的每个周期表示施加到级的所述时钟节点的时钟信号的N个周期， 输出信号具有比所述时钟信号的占空比更接近于50％的占空比。

公开(公告)号：US6097783A

公开(公告)日：2000-08-01

申请号：US221669

申请日：1998-12-23

Applicant: Trevor Monk

Inventor： Trevor Monk

IPC: H03K23/44 ,  H03K23/54 ,  H03K23/66 ,  H03L7/183 ,  H03K21/00

CPC classification number: H03K23/66 ,  H03K23/44 ,  H03K23/54 ,  H03K23/667 ,  H03L7/183

Abstract: A dividing circuit comprises, connected in a ring, a plurality M of transistor stages, where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage has an input node connected to the output node of a preceding transistor stage in the ring, an enable node connected to the clock nodes of the transistor stages, and an output node connected to the input node of a subsequent transistor stage in the ring. Each transistor stage comprises a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node, and a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, wherein control nodes of a first transistor of each said transistor pair are connected together to provide the input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide the clock node for the stage, whereby when an input clock signal is applied to the clock nodes of the transistor stages, an output signal is generated at the output node of the tri-state inverter in which each cycle represents M cycles of the input clock signal.

Abstract translation: 分频电路包括以环形连接多个M个晶体管级，其中M为偶数整数。 每个晶体管级包括输入节点，时钟节点和输出节点。 三态逆变器级具有连接到环中先前晶体管级的输出节点的输入节点，连接到晶体管级的时钟节点的使能节点和连接到后续晶体管的输入节点的输出节点 在戒指阶段。 每个晶体管级包括串联连接在第一电压电平和输出节点之间的第一导电类型的第一对晶体管，以及串联连接在第二电压电平和所述输出节点之间的第二导电类型的第二对晶体管 其中，每个所述晶体管对的第一晶体管的控制节点连接在一起以提供所述级的输入节点，并且每个所述晶体管对的第二晶体管的控制节点连接在一起以为所述级提供所述时钟节点，由此 当输入时钟信号施加到晶体管级的时钟节点时，在三态反相器的输出节点处产生输出信号，其中每个周期表示输入时钟信号的M个周期。

公开(公告)号：US5731714A

公开(公告)日：1998-03-24

申请号：US535876

申请日：1995-09-28

Applicant: Trevor Monk ,  Curtis Dicke

Inventor： Trevor Monk ,  Curtis Dicke

IPC: H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00361 ,  H03K17/165

Abstract: An off-chip driver circuit can operate in an output mode to drive a signal supplied at its input terminals to an output terminal. It can also operate in an input mode in which signals are driven from an external circuit via the output terminal onto the chip. In an output mode, the output terminal is clamped to reduce the effect of overshoot voltages, for example as a result of reflections from the external circuits.

Abstract translation: 片外驱动电路可以在输出模式下工作，以将其输入端提供的信号驱动到输出端。 它也可以在信号通过输出端从外部电路驱动到芯片上的输入模式下工作。 在输出模式中，输出端子被钳位以减小过冲电压的影响，例如作为来自外部电路的反射的结果。

公开(公告)号：US5729157A

公开(公告)日：1998-03-17

申请号：US506879

申请日：1995-07-25

Applicant: Trevor Monk ,  Curtis Dicke

Inventor： Trevor Monk ,  Curtis Dicke

IPC: H03K19/003 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0948

CPC classification number: H03K19/00315 ,  H03K19/09429 ,  H03K19/09485

Abstract: An off-chip driver circuit having circuitry for providing protection against high voltages when the off-chip driver circuit is disabled is described. The circuitry for providing protection against high voltages utilizes a minimum number of transistors and therefore minimizes the chip area utilized by the off-chip driver circuit. An off-chip driver circuit has an input terminal and an output terminal. A pull-up transistor has a controllable path connected between a first power supply voltage and the output terminal of the off-chip driver circuit, and a control terminal connected to the input terminal via a pass gate connected to isolate the input terminal from high voltages applied to the output terminal. A control transistor has a controllable path connected between the control terminal of the pull-up transistor and the output terminal, and a control terminal connected to a control potential. An auxiliary pass transistor has a control terminal and a controllable path connected between a reference terminal and the control terminal of the pull-up transistor. An auxiliary control transistor has a control terminal connected to receive the control potential, and a controllable path connected between the output terminal and the control terminal of the auxiliary pass transistor. Auxiliary circuitry holds the control terminal of the auxiliary pass transistor in a state determined by the auxiliary control transistor. The auxiliary circuitry may include an auxiliary pull-down transistor having a controllable path connected between the control terminal of the auxiliary pass transistor and a reference potential, and a control terminal connected to a voltage selected to maintain the auxiliary pull-down transistor on.

Abstract translation: 描述了片外驱动器电路，其具有用于在片外驱动器电路被禁用时提供高电压保护的电路。 用于提供高电压保护的电路利用最小数量的晶体管，因此最小化片外驱动电路所使用的芯片面积。 片外驱动电路具有输入端和输出端。 上拉晶体管具有连接在第一电源电压和片外驱动电路的输出端之间的可控路径，以及连接到输入端的控制端，该通路被连接以将输入端与高电压隔离 应用于输出端子。 控制晶体管具有连接在上拉晶体管的控制端和输出端之间的可控路径，以及连接到控制电位的控制端。 辅助通过晶体管具有连接在参考端和上拉晶体管的控制端之间的控制端和可控路径。 辅助控制晶体管具有连接以接收控制电位的控制端子和连接在辅助传输晶体管的输出端子和控制端子之间的可控路径。 辅助电路将辅助通过晶体管的控制端子保持在由辅助控制晶体管确定的状态。 辅助电路可以包括辅助下拉晶体管，其具有连接在辅助传输晶体管的控制端子和参考电位之间的可控路径，以及连接到选择用于维持辅助下拉晶体管导通的电压的控制端子。