公开(公告)号：US07162613B2

公开(公告)日：2007-01-09

申请号：US11046454

申请日：2005-01-28

申请人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark H. Pearce ,  Zongjian Chen

发明人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark H. Pearce ,  Zongjian Chen

IPC分类号： G06F9/312

CPC分类号： G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3867

摘要： A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.

摘要翻译： 一种处理器包括第一电路和第二电路。 第一电路被配置为提供在处理器中至少一个预留是否有效的第一指示。 响应于处理负载链接指令来建立预留，负载指令是建筑上定义用于建立预留的加载指令。 有效的预约指示由保留建立以来，由负载链接指令的目标地址指示的一个或多个字节未被更新。 第二电路被耦合以接收第一指示。 响应于第一指示，不指示有效预约，第一电路被配置为选择用于发出的推测性加载链接指令。 第二电路被配置为不响应于指示至少一个有效预留的第一指示来选择用于发出的推测性加载链接指令。 也考虑了一种方法。

公开(公告)号：US06877085B2

公开(公告)日：2005-04-05

申请号：US10068286

申请日：2002-02-06

申请人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark H. Pearce ,  Zongjian Chen

发明人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark H. Pearce ,  Zongjian Chen

IPC分类号： G06F9/312 ,  G06F9/38

CPC分类号： G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3867

摘要： A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.

摘要翻译： 处理器包括第一电路和第二电路。 第一电路被配置为提供在处理器中至少一个预留是否有效的第一指示。 响应于处理负载链接指令来建立预留，负载指令是建筑上定义用于建立预留的加载指令。 有效的预约指示由保留建立以来，由负载链接指令的目标地址指示的一个或多个字节未被更新。 第二电路被耦合以接收第一指示。 响应于第一指示，不指示有效预约，第一电路被配置为选择用于发出的推测性加载链接指令。 第二电路被配置为不响应于指示至少一个有效预留的第一指示来选择用于发出的推测性加载链接指令。 也考虑了一种方法。

公开(公告)号：US20050154862A1

公开(公告)日：2005-07-14

申请号：US11046454

申请日：2005-01-28

申请人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark Pearce ,  Zongjian Chen

发明人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark Pearce ,  Zongjian Chen

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3867

摘要： A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.

摘要翻译： 处理器包括第一电路和第二电路。 第一电路被配置为提供在处理器中至少一个预留是否有效的第一指示。 响应于处理负载链接指令来建立预留，负载指令是建筑上定义用于建立预留的加载指令。 有效的预约指示由保留建立以来，由负载链接指令的目标地址指示的一个或多个字节未被更新。 第二电路被耦合以接收第一指示。 响应于第一指示，不指示有效预约，第一电路被配置为选择用于发出的推测性加载链接指令。 第二电路被配置为不响应于指示至少一个有效预留的第一指示来选择用于发出的推测性加载链接指令。 也考虑了一种方法。

公开(公告)号：US08566627B2

公开(公告)日：2013-10-22

申请号：US12502685

申请日：2009-07-14

申请人： Sameer Halepete ,  H. Peter Anvin ,  Zongjian Chen ,  Godfrey P. D'Souza ,  Marc Fleischmann ,  Keith Klayman ,  Thomas Lawrence ,  Andrew Read

发明人： Sameer Halepete ,  H. Peter Anvin ,  Zongjian Chen ,  Godfrey P. D'Souza ,  Marc Fleischmann ,  Keith Klayman ,  Thomas Lawrence ,  Andrew Read

IPC分类号： G06F1/00 ,  H03L7/00

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

公开(公告)号：US08417844B2

公开(公告)日：2013-04-09

申请号：US13474373

申请日：2012-05-17

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US08045472B2

公开(公告)日：2011-10-25

申请号：US12344949

申请日：2008-12-29

申请人： James Wang ,  Zongjian Chen

发明人： James Wang ,  Zongjian Chen

IPC分类号： H04L12/26

CPC分类号： G06F13/385 ,  H04L47/10 ,  H04L47/39 ,  H04L49/90

摘要： In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes.

摘要翻译： 在一个实施例中，基于信用的流量控制接口上的接收器被配置为在接收到数据有效载荷时释放一个或多个数据信息，该数据有效载荷在缓冲存储器内产生更少的未被使用的数据信用，该缓冲存储器以比该 数据信用。 在另一个实施例中，基于实际分组数据有效载荷大小动态地调整报头信用和数据信用。

公开(公告)号：US20110010502A1

公开(公告)日：2011-01-13

申请号：US12500768

申请日：2009-07-10

申请人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

发明人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/128 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/123

摘要： In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

摘要翻译： 在一个实施例中，高速缓存存储存储在高速缓存中的高速缓存块的标签。 每个标签可以包括标识由高速缓存支持的两个或多个替换策略中哪一个正在用于对应的高速缓存块的指示，以及指示替换策略中对应的高速缓存块的状态的替换记录。 请求可以包括标识用于请求访问的高速缓存块的期望替换策略的替换属性。 如果请求是高速缓存中的错过，则可以分配高速缓存块存储位置以存储相应的高速缓存块。 与高速缓存块存储位置相关联的标签可以被更新以包括期望的替换策略的指示，并且高速缓存可以根据策略来管理块。 例如，在一个实施例中，高速缓存可以支持LRR和LRU策略。

公开(公告)号：US20070162652A1

公开(公告)日：2007-07-12

申请号：US11682065

申请日：2007-03-05

申请人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US08566485B2

公开(公告)日：2013-10-22

申请号：US13566485

申请日：2012-08-03

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US08078772B2

公开(公告)日：2011-12-13

申请号：US12908605

申请日：2010-10-20

申请人： James Wang ,  Zongjian Chen ,  James B. Keller

发明人： James Wang ,  Zongjian Chen ,  James B. Keller

IPC分类号： G06F13/00 ,  H03K5/135

CPC分类号： G06F5/14

摘要： In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.