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    Restoring processor context in response to processor power-up
    6.
    发明授权
    Restoring processor context in response to processor power-up 有权
    响应处理器上电恢复处理器上下文

    公开(公告)号：US08140872B1

    公开(公告)日：2012-03-20

    申请号：US12136679

    申请日：2008-06-10

    申请人： Marc Fleischmann ,  H. Peter Anvin

    发明人： Marc Fleischmann ,  H. Peter Anvin

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3234 ,  G06F1/3228 ,  G06F1/3246 ,  G06F9/4418 ,  Y02D10/44 ,  Y02D50/20

    摘要： A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.

    摘要翻译： CPU（1）会在CPU在休眠模式下关闭电源时自动保留计算机内存（5）中的CPU上下文，该内存保持加电。 通过保留的CPU上下文，CPU能够在CPU断电时被断言执行的程序的指令瞬间和透明地恢复程序执行。 即使在执行程序期间，也可以频繁地断电CPU，从而降低平均总功耗。

    System and method for saving and restoring a processor state without executing any instructions from a first instruction set
    8.
    发明授权
    System and method for saving and restoring a processor state without executing any instructions from a first instruction set 有权
    用于保存和恢复处理器状态而不执行来自第一指令集的任何指令的系统和方法

    公开(公告)号：US07730330B1

    公开(公告)日：2010-06-01

    申请号：US11201624

    申请日：2005-08-10

    申请人： Marc Fleischmann ,  H. Peter Anvin

    发明人： Marc Fleischmann ,  H. Peter Anvin

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3234 ,  G06F1/3228 ,  G06F1/3246 ,  G06F9/4418 ,  Y02D10/44 ,  Y02D50/20

    摘要： A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.

    摘要翻译： CPU（1）会在CPU在休眠模式下关闭电源时自动保留计算机内存（5）中的CPU上下文，该内存保持加电。 通过保留的CPU上下文，CPU能够在CPU断电时被断言执行的程序的指令瞬间和透明地恢复程序执行。 即使在执行程序期间，也可以频繁地断电CPU，从而降低平均总功耗。

    STORING CONTEXT INFORMATION PRIOR TO NOT SUPPLYING POWER TO A PROCESSOR
    9.
    发明申请
    STORING CONTEXT INFORMATION PRIOR TO NOT SUPPLYING POWER TO A PROCESSOR 审中-公开
    存在未向供应商提供电力的上下文信息

    公开(公告)号：US20120210155A1

    公开(公告)日：2012-08-16

    申请号：US13370241

    申请日：2012-02-09

    申请人： Marc Fleischmann ,  H. Peter Anvin

    发明人： Marc Fleischmann ,  H. Peter Anvin

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3234 ,  G06F1/3228 ,  G06F1/3246 ,  G06F9/4418 ,  Y02D10/44 ,  Y02D50/20

    摘要： A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.

    摘要翻译： CPU（1）会在CPU在休眠模式下关闭电源时自动保留计算机内存（5）中的CPU上下文，该内存保持加电。 通过保留的CPU上下文，CPU能够在CPU断电时被断言执行的程序的指令瞬间和透明地恢复程序执行。 即使在执行程序期间，也可以频繁地断电CPU，从而降低平均总功耗。

    Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine
    10.
    发明授权
    Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine 有权
    为虚拟机提供内存保护和虚拟内存地址转换的硬件支持的方法和系统

    公开(公告)号：US08041876B1

    公开(公告)日：2011-10-18

    申请号：US11500575

    申请日：2006-08-07

    申请人： H. Peter Anvin

    发明人： H. Peter Anvin

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1027 ,  G06F12/1036 ,  G06F12/145

    摘要： A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context are stored within a TLB. Memory protection bits for the plurality of TLB entries are logically combined to enforce memory protection on the virtual machine application.

    摘要翻译： 一种为虚拟机提供内存保护和虚拟内存地址转换的硬件支持的方法。 该方法包括在主机上下文中执行主机应用并且在虚拟机上下文中执行虚拟机应用。 用于虚拟机上下文和主机上下文的多个TLB（转换后备缓冲器）条目存储在TLB内。 逻辑上组合用于多个TLB条目的存储器保护位以在虚拟机应用上实现存储器保护。