公开(公告)号：US06683352B2

公开(公告)日：2004-01-27

申请号：US10078314

申请日：2002-02-15

申请人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L2976

CPC分类号： H01L21/823425 ,  H01L21/823443 ,  H01L29/4238 ,  H01L29/665

摘要： A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.

摘要翻译： 公开了一种金属氧化物半导体场效应晶体管结构。 p型栅极，设置在半导体衬底上。 栅极电介质层设置在p型栅极和半导体衬底之间。 漏极区域设置在半导体衬底内，其中漏极区域被p型栅极包围。 源极区域设置在半导体衬底内，其中源极区域围绕p形栅极。 在源极/漏极区域和p形栅极上设置硅化物结构。

公开(公告)号：US06549029B1

公开(公告)日：2003-04-15

申请号：US09990261

申请日：2001-11-20

申请人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G01R3126

CPC分类号： G01R27/2605

摘要： A circuit structure for measuring a capacitive load. The capacitive load is coupled between a first and a second nodes, and drains of a first PMOS and a first NMOS transistors are coupled to the first node, and drains of a second PMOS and a second NMOS transistors are coupled to the second node, and a pad is coupled to the second node. First, sources of the first and the second PMOS transistors and sources of the first and the second NMOS transistors are biased at a power source and a ground respectively. A non-synchronized voltage is applied to gates of the first and the second PMOS transistors and to gates of the first and the second NMOS transistors simultaneously. By grounding and floating the pad, a current flowing through the capacitive load is obtained to calculate the capacitance.

摘要翻译： 用于测量电容性负载的电路结构。 电容性负载耦合在第一和第二节点之间，并且第一PMOS和第一NMOS晶体管的漏极耦合到第一节点，并且第二PMOS和第二NMOS晶体管的漏极耦合到第二节点，并且 垫连接到第二节点。 首先，第一和第二PMOS晶体管的源极和第一和第二NMOS晶体管的源极分别偏置在电源和地。 非同步电压同时施加到第一和第二PMOS晶体管的栅极和第一和第二NMOS晶体管的栅极。 通过接地和浮动焊盘，获得流过电容性负载的电流来计算电容。

公开(公告)号：US08952484B2

公开(公告)日：2015-02-10

申请号：US12949092

申请日：2010-11-18

申请人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L21/70 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/792 ,  H01L21/76232

摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.

摘要翻译： 提供了一种非易失性存储器及其制造方法。 非挥发性存储器包括衬底，栅极结构，第一掺杂区，第二掺杂区和一对隔离结构。 栅极结构设置在基板上。 栅极结构包括电荷存储结构，栅极和间隔物。 电荷存储结构设置在基板上。 栅极设置在电荷存储结构上。 间隔件设置在栅极和电荷存储结构的侧壁上。 第一掺杂区域和第二掺杂区域分别设置在电荷存储结构的两侧的基板中，并且至少位于间隔物之下。 隔离结构分别设置在栅极结构的两侧的基板中。

公开(公告)号：US20120287539A1

公开(公告)日：2012-11-15

申请号：US13105270

申请日：2011-05-11

申请人： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection device electronically connected to a pad is provided. The ESD protection device includes K PNP transistors and a protection circuit, wherein K is a positive integer. An emitter of the 1st PNP transistor is electronically connected to the pad, a base of the ith PNP transistor is electronically connected to an emitter of the (i+1)th PNP transistor, and collectors of the K PNP transistors are electronically connected to a ground, wherein i is an integer and 1≦i≦(K−1). The protection circuit is electronically connected between a base of the Kth PNP transistor and the ground and provides a discharge path. An electrostatic signal from the pad is conducted to the ground through the discharge path and the K PNP transistors.

摘要翻译： 提供电连接到垫的静电放电（ESD）保护装置。 ESD保护装置包括K PNP晶体管和保护电路，其中K是正整数。 第一PNP晶体管的发射极电连接到焊盘，第i PNP晶体管的基极电连接到第（i + 1）PNP晶体管的发射极，并且K PNP晶体管的集电极电连接到 地面，其中i是整数，1＆nlE; i＆nlE;（K-1）。 保护电路电连接在第K PNP晶体管的基极与地之间并提供放电路径。 来自焊盘的静电信号通过放电路径和K PNP晶体管传导到地面。

公开(公告)号：US08203879B2

公开(公告)日：2012-06-19

申请号：US12834233

申请日：2010-07-12

申请人： Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404

摘要： An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting a main voltage distribution group and a plurality of secondary voltage distribution groups, wherein each of the main voltage distribution group and the secondary voltage distribution groups includes N threshold-voltage distribution curves, and N is an integer greater than 2; selecting a first operation level and a second operation level according to a programming command; programming the first storage position according to the threshold-voltage distribution curve corresponding to the first operation level in the main voltage distribution group; selecting one of the secondary voltage distribution groups according to the first operation level and programming the second storage position according to the threshold-voltage distribution curve corresponding to the second operation level in the selected secondary voltage distribution group.

摘要翻译： 提供适用于具有第一存储位置和第二存储位置的多级单元的非易失性存储器的操作方法。 操作方法包括：设置主电压分配组和多个次级电压分布组，其中主电压分配组和次级电压分配组中的每一个包括N个阈值电压分布曲线，并且N是大于2的整数 ; 根据编程命令选择第一操作级别和第二操作级别; 根据与主电压分配组中的第一操作电平相对应的阈值电压分布曲线对第一存储位置进行编程; 根据第一操作电平选择二次电压分配组中的一个，并根据与所选次级电压分配组中的第二操作电平对应的阈值电压分布曲线对第二存储位置进行编程。

公开(公告)号：US08098522B2

公开(公告)日：2012-01-17

申请号：US12574093

申请日：2009-10-06

申请人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/3468 ,  G11C16/0466 ,  G11C16/10

摘要： An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1st level and an auxiliary level respectively according to the 1st threshold-voltage distribution curve and a threshold-voltage auxiliary curve when the first and the second storage positions are programmed to the 1st and Nth levels; and programming the first and the second storage positions to the ith level according to the ith threshold-voltage distribution curve when the first and the second storage positions are not to be programmed to the 1st and Nth levels, wherein i is an integer and 1≦i≦N.

摘要翻译： 提供适用于具有第一存储位置和第二存储位置的多级单元的非易失性存储器的操作方法。 操作方法包括：设置N个阈值电压分布曲线，其中N个阈值电压分布曲线对应于N个电平，N是大于2的整数; 当第一和第二存储位置被编程到第1和第N级时，分别根据第一阈值电压分布曲线和阈值电压辅助曲线将第一和第二存储位置编程到第一级和辅助级; 以及当所述第一和第二存储位置不被编程到所述第一和第N电平时，根据所述第i阈值电压分布曲线将所述第一和第二存储位置编程为第i级，其中i是整数和1＆nlE; 我＆nlE; N。

公开(公告)号：US20110182123A1

公开(公告)日：2011-07-28

申请号：US12834228

申请日：2010-07-12

申请人： GUAN-WEI WU ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： GUAN-WEI WU ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336 ,  H01L29/78 ,  G11C16/16

CPC分类号： H01L29/792 ,  G11C16/0475 ,  H01L29/4234 ,  H01L29/42352

摘要： A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion.

摘要翻译： 提供闪速存储器及其制造方法及其操作方法。 闪速存储器包括衬底，电荷俘获结构，第一栅极，第二栅极，第三栅极，第一掺杂区域和第二掺杂区域。 基板具有突起部。 电荷捕获结构设置在衬底上。 第一栅极和第二栅极分别设置在突出部分的两侧的电荷捕获结构的上方。 第一栅极和第二栅极的顶表面比位于突起部分顶部的电荷捕获结构的顶表面低。 第三栅极设置在位于突起部分的顶部上的电荷捕获结构之上。 第一掺杂区域和第二掺杂区域分别设置在基板的突出部分的两侧。

公开(公告)号：US20100302855A1

公开(公告)日：2010-12-02

申请号：US12614647

申请日：2009-11-09

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu ,  Guan-Wei Wu ,  Tao-Yuan Lin ,  Po-Chou Chen

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu ,  Guan-Wei Wu ,  Tao-Yuan Lin ,  Po-Chou Chen

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336

CPC分类号： G11C16/0475 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

摘要： The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.

摘要翻译： 描述了存储器件，其包括衬底，导电层，多个电荷存储层和多个掺杂区域。 衬底具有形成在其中的多个沟槽。 导电层设置在基板上并填充沟槽。 电荷存储层分别设置在沟槽中的衬底和导电层之间，其中电荷存储层彼此分离。 掺杂区域分别配置在沟槽底部的衬底中。

公开(公告)号：US07486086B2

公开(公告)日：2009-02-03

申请号：US11979576

申请日：2007-11-06

申请人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G01R27/26

CPC分类号： G01R31/2621

摘要： A method for measuring intrinsic capacitance of a MOS device is provided. The MOS device includes a first terminal, a second terminal, a third terminal and a fourth terminal. First, provide a first input signal to the second terminal and ground the third terminal and fourth terminal. Then, charge the first terminal and measure a first current required for charging the first terminal. Afterward, provide a second input signal to the second terminal, ground the third terminal and the fourth terminal, and measure a second current required for charging the first terminal, wherein the first input signal and the second input signal have the same low level, but different high levels. Finally, determine intrinsic capacitance between the first terminal and the second terminal according to the first current, the second current and a high level difference between the first input signal and the second input signal.

摘要翻译： 提供了一种用于测量MOS器件的本征电容的方法。 MOS器件包括第一端子，第二端子，第三端子和第四端子。 首先，向第二终端提供第一输入信号，并将第三终端和第四终端接地。 然后，对第一终端充电并测量对第一终端充电所需的第一电流。 然后，向第二终端提供第二输入信号，将第三端子和第四端子接地，并测量对第一端子充电所需的第二电流，其中第一输入信号和第二输入信号具有相同的低电平，但是 不同的高层次。 最后，根据第一电流，第二电流和第一输入信号与第二输入信号之间的高电平差来确定第一端子和第二端子之间的本征电容。

公开(公告)号：US20080080251A1

公开(公告)日：2008-04-03

申请号：US11905211

申请日：2007-09-28

申请人： Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/28

摘要： A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value.

摘要翻译： 读取双位存储单元的方法包括控制终端，第一终端和第二终端。 双位存储单元分别具有第一位存储节点和靠近第一终端和第二终端的第二位存储节点。 首先，分别对控制端子和第一端子施加控制电压和读取电压。 第二端子接地以测量第一端子的第一输出电流值。 然后，控制电压和读取电压分别施加到控制端子和第二端子。 第一端子接地以测量第二端子的第二输出电流值。 之后，根据第一输出电流值和第二输出电流值同时读取第一位存储节点的位状态和第二位存储节点的位状态。