Deinterleaver and dual-viterbi decoder architecture
    1.
    发明授权
    Deinterleaver and dual-viterbi decoder architecture 有权
    去交织器和双维特比解码器架构

    公开(公告)号:US07779338B2

    公开(公告)日:2010-08-17

    申请号:US11490844

    申请日:2006-07-21

    IPC分类号: H03M13/03

    摘要: Pairs of parallel Viterbi decoders use windowed block data for decoding data at rates above 320 Mbps. Memory banks of the deinterleavers feeding the decoders operate such that some are receiving data while others are sending data to the decoders. Parallel input streams to every pair of decoders overlap for several traceback lengths of the decoder causing data input to a first decoder at the end of an input stream to be the same as the data input to a second decoder of the same pair at the beginning of an input stream. Then, the first decoder is able to post-synchronize its path metric with the second decoder and the second decoder is able to pre-synchronize its path metric with the first. Either, the deinterleaver data length is an integer multiple of the traceback length or the data input to only the first block of the first interleaver is padded.

    摘要翻译: 一对并行维特比解码器使用窗口块数据,以高于320 Mbps的速率解码数据。 供给解码器的解交织器的存储器操作,使得一些接收数据,而其他数据传送到解码器。 对于每对解码器的并行输入流与解码器的几个回溯长度重叠,导致在输入流结束时输入到第一解码器的数据输入与输入到相同对的第二解码器的数据相同 一个输入流。 然后,第一解码器能够与第二解码器后同步其路径度量,并且第二解码器能够将其路径度量与第一解码器预先同步。 或者,解交织器数据长度是回溯长度的整数倍,或仅填充第一交织器的第一块的数据输入。

    Dynamic AC-coupled DC offset correction
    2.
    发明申请
    Dynamic AC-coupled DC offset correction 有权
    动态AC耦合直流偏移校正

    公开(公告)号:US20050260967A1

    公开(公告)日:2005-11-24

    申请号:US10850774

    申请日:2004-05-21

    申请人: Turgut Aytur

    发明人: Turgut Aytur

    IPC分类号: H04B1/10 H04B1/30

    CPC分类号: H04B1/30

    摘要: Methods and systems that utilize AC-coupled filtering to reduce DC offset, with aspects dynamically correcting instantaneous DC offset generated from the AC-coupled filtering. A DC offset correction circuit for an radio frequency (rf) receiver comprises a switchable high pass filter receiving a downconverted rf signal. The switchable high pass filter has N selectable corner frequencies, where N is greater than two.

    摘要翻译: 利用交流耦合滤波来减少直流偏移的方法和系统,方面动态校正从交流耦合滤波产生的瞬时直流偏移。 用于射频(rf)接收机的DC偏移校正电路包括接收下变频RF信号的可切换高通滤波器。 可切换高通滤波器具有N个可选转角频率,其中N大于2。

    CHANNEL ESTIMATION
    3.
    发明申请
    CHANNEL ESTIMATION 有权
    频道估计

    公开(公告)号:US20070280366A1

    公开(公告)日:2007-12-06

    申请号:US11757247

    申请日:2007-06-01

    IPC分类号: H04K1/10

    摘要: A receiver including a channel estimation function in which an initial channel estimate is filtered to increase receiver operation, particularly when the receiver may only have a limited number of channel estimation symbols with which to form the channel estimate. In some embodiments the filtering is performed by transforming the initial channel estimate to the time domain, zeroing some of the samples to filter the time domain channel estimate, and transforming the filtered time domain channel estimate to the frequency domain for use in channel compensation.

    摘要翻译: 一种包括信道估计功能的接收机,其中对初始信道估计进行滤波以增加接收机操作,特别是当接收机只能具有用于形成信道估计的有限数量的信道估计符号时。 在一些实施例中,通过将初始信道估计变换到时域来执行滤波,对某些采样进行归零以对时域信道估计进行滤波,并将经滤波的时域信道估计变换到频域以用于信道补偿。

    Deinterleaver and dual-viterbi decoder architecture
    4.
    发明申请
    Deinterleaver and dual-viterbi decoder architecture 有权
    去交织器和双维特比解码器架构

    公开(公告)号:US20070067704A1

    公开(公告)日:2007-03-22

    申请号:US11490844

    申请日:2006-07-21

    IPC分类号: H03M13/03

    摘要: Pairs of parallel Viterbi decoders use windowed block data for decoding data at rates above 320 Mbps. Memory banks of the deinterleavers feeding the decoders operate such that some are receiving data while others are sending data to the decoders. Parallel input streams to every pair of decoders overlap for several traceback lengths of the decoder causing data input to a first decoder at the end of an input stream to be the same as the data input to a second decoder of the same pair at the beginning of an input stream. Then, the first decoder is able to post-synchronize its path metric with the second decoder and the second decoder is able to pre-synchronize its path metric with the first. Either, the deinterleaver data length is an integer multiple of the traceback length or the data input to only the first block of the first interleaver is padded.

    摘要翻译: 一对并行维特比解码器使用窗口块数据,以高于320 Mbps的速率解码数据。 供给解码器的解交织器的存储器操作,使得一些接收数据,而其他数据传送到解码器。 对于每对解码器的并行输入流与解码器的几个回溯长度重叠,导致在输入流结束时输入到第一解码器的数据输入与输入到相同对的第二解码器的数据相同 一个输入流。 然后,第一解码器能够与第二解码器后同步其路径度量,并且第二解码器能够将其路径度量与第一解码器预先同步。 或者,解交织器数据长度是回溯长度的整数倍,或仅填充第一交织器的第一块的数据输入。

    Packet detection
    5.
    发明授权
    Packet detection 有权
    数据包检测

    公开(公告)号:US08457162B2

    公开(公告)日:2013-06-04

    申请号:US11506193

    申请日:2006-08-16

    IPC分类号: H04J3/06

    摘要: An apparatus for and a method of performing packet detection in a receiver is provided. The apparatus is configured to determine a measure of a correlation between information of one or more received symbols and synchronization information. The apparatus is also configured to determine a measure of an energy value of one or more of the received symbols. The apparatus is also configured to determine if a packet has been detected based on the measure of the correlation and the measure of the energy value of the one or more received symbols.

    摘要翻译: 提供了一种用于在接收机中执行分组检​​测的装置和方法。 该装置被配置为确定一个或多个接收到的符号的信息与同步信息之间的相关性的度量。 该装置还被配置为确定一个或多个接收符号的能量值的度量。 该装置还被配置为基于相关性的测量和一个或多个接收符号的能量值的测量来确定是否已经检测到分组。

    Dynamic AC-Coupled DC Offset Correction
    6.
    发明申请
    Dynamic AC-Coupled DC Offset Correction 审中-公开
    动态AC耦合直流偏移校正

    公开(公告)号:US20120238231A1

    公开(公告)日:2012-09-20

    申请号:US13461981

    申请日:2012-05-02

    申请人: Turgut Aytur

    发明人: Turgut Aytur

    IPC分类号: H04B1/10

    CPC分类号: H04B1/30

    摘要: A method, using an AC-coupled filter, reduces DC offset in a downconverted signal in a wireless receiver receiving a signal including a preamble, the method including: changing the corner frequency of the AC-coupled filter a plurality of times during reception of the preamble. In another implementation, a receiver includes a DC offset correction system. The receiver includes a mixer downconverting a received signal to form a downconverted signal; a first AC-coupled high pass filter having an input in at least one-way data communication with the mixer, the first AC-coupled high pass filter having a switchable corner frequency dependent on a frame state of a received signal; and a plurality of second AC-coupled high pass filters coupled to an output of the first AC-coupled high pass filter, each of the plurality of second AC-coupled high pass filters have a switchable corner frequency.

    摘要翻译: 使用AC耦合滤波器的方法减少了在接收包括前导码的信号的无线接收机中的下变频信号中的DC偏移,所述方法包括:在接收到所述AC耦合滤波器的接收期间多次改变AC耦合滤波器的转角频率 前言。 在另一实现中,接收机包括DC偏移校正系统。 接收机包括下变频接收信号以形成下变频信号的混频器; 第一AC耦合高通滤波器,其具有与混频器的至少单向数据通信的输入,第一AC耦合高通滤波器具有取决于接收信号的帧状态的可切换转角频率; 以及耦合到所述第一交流耦合高通滤波器的输出的多个第二AC耦合高通滤波器,所述多个第二AC耦合高通滤波器中的每一个具有可切换的转角频率。

    Dynamic AC-Coupled DC Offset Correction
    7.
    发明申请
    Dynamic AC-Coupled DC Offset Correction 有权
    动态AC耦合直流偏移校正

    公开(公告)号:US20120220249A1

    公开(公告)日:2012-08-30

    申请号:US13461952

    申请日:2012-05-02

    申请人: Turgut Aytur

    发明人: Turgut Aytur

    IPC分类号: H04B1/18

    CPC分类号: H04B1/30

    摘要: Systems are disclosed that utilize AC-coupled filtering to reduce DC offset, with aspects dynamically correcting instantaneous DC offset generated from the AC-coupled filtering. A DC offset correction circuit for an radio frequency (rf) receiver, comprising a switchable high pass filter configured to receive a signal, the switchable high pass filter including a plurality of high pass filters connected in parallel, wherein at least one of the plurality of high pass filters has a tunable corner frequency.

    摘要翻译: 公开了利用AC耦合滤波来减少DC偏移的系统,其中动态地校正从AC耦合滤波产生的瞬时DC偏移。 一种用于射频(rf)接收机的DC偏移校正电路,包括被配置为接收信号的可切换高通滤波器,所述可切换高通滤波器包括并联连接的多个高通滤波器,其中所述多个 高通滤波器具有可调转角频率。

    Automatic gain control for frequency-hopped OFDM
    8.
    发明授权
    Automatic gain control for frequency-hopped OFDM 有权
    跳频OFDM自动增益控制

    公开(公告)号:US08254480B2

    公开(公告)日:2012-08-28

    申请号:US13044157

    申请日:2011-03-09

    IPC分类号: H04K1/10 H04L27/28

    摘要: An automatic gain control method and system for use in signal processing of OFDM symbols at a receiver. Two stages of coarse and fine automatic gain control are implemented that adjust different gains in an analog RF processing stage of the receiver. Gain of a low noise amplifier and a mixer are adjusted during a first and coarse automatic gain control stage based on feedback from a digital baseband stage. During a subsequent fine gain control period, the gain of a programmable gain amplifier is adjusted separately for each frequency band used by the OFDM symbols based on a histogram bin that counts the number of output samples of an analog to digital converter whose magnitude falls within certain ranges. Coarse and fine gains are updated after each OFDM symbol.

    摘要翻译: 一种用于在接收机处对OFDM符号进行信号处理的自动增益控制方法和系统。 实现两级粗略和精细的自动增益控制,可在接收机的模拟RF处理阶段调整不同的增益。 基于来自数字基带级的反馈,在第一和粗略的自动增益控制级中调整低噪声放大器和混频器的增益。 在随后的精细增益控制周期期间,可编程增益放大器的增益分别针对由OFDM符号使用的每个频带进行调整,所述频带基于对其幅度在一定范围内的模数转换器的输出样本数进行计数的直方图单元 范围。 在每个OFDM符号之后更新粗和细增益。

    CMOS transceiver for communication system
    9.
    发明授权
    CMOS transceiver for communication system 有权
    CMOS收发器用于通信系统

    公开(公告)号:US07986726B2

    公开(公告)日:2011-07-26

    申请号:US11267829

    申请日:2005-11-03

    IPC分类号: H04B1/38

    摘要: A direct conversion ultrawideband transceiver employing three phase locked loops (PLLs). The PLLs are preferably fixed-frequency PLLs that operate continuously, at different frequencies, with a selected frequency determined by selecting the output of one of the three PLLs. The use of three PLLs is suitable for use in a communication system employing frequency hopping across three bands or sub-bands.

    摘要翻译: 采用三个锁相环(PLL)的直接转换超宽带收发器。 PLL优选地是以不同频率连续工作的固定频率PLL,选择的频率是通过选择三个PLL之一的输出来确定的。 使用三个PLL适用于在三个频带或子频带上采用跳频的通信系统。

    Pre-association for CWUSB
    10.
    发明授权
    Pre-association for CWUSB 有权
    CWUSB预协会

    公开(公告)号:US07865642B2

    公开(公告)日:2011-01-04

    申请号:US12272287

    申请日:2008-11-17

    IPC分类号: G06F13/42 G06F13/00

    摘要: Certified Wireless USB 1.0 defines two different types of association: cable association and numeric association. In order to implementation these two association methods, the CWUSB device needs to have either upstream USB connector (for cable association) or display capability (for numeric association). These extra requirements make the CWUSB device bulkier (one more USB connector) and/or more expensive (extra display components). For cheap and simple CWUSB devices, we need a simpler association method that is easy and cheap to implement. In a pre-packaged total solution, which includes a host and one or more device(s), we can use pre-association to smooth the user experience. The host and device(s) are pre-associated. When an end user starts to use this solution, they do not need to worry about the association at all.

    摘要翻译: 认证无线USB 1.0定义了两种不同类型的关联:电缆关联和数字关联。 为了实现这两种关联方法,CWUSB设备需要有上游USB连接器(用于电缆关联)或显示功能(用于数字关联)。 这些额外的要求使得CWUSB设备体积更大(一个USB连接器)和/或更昂贵的(额外的显示组件)。 对于便宜和简单的CWUSB设备,我们需要一种简单易用的关联方法来实现。 在包括主机和一个或多个设备的预先打包的整体解决方案中,我们可以使用预关联来平滑用户体验。 主机和设备是预先关联的。 最终用户开始使用这种解决方案时,他们根本不用担心关联。