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196 条记录 (耗时 0.021 秒)

    Refreshing memory cells of a phase change material memory device
    1.
    发明授权
    Refreshing memory cells of a phase change material memory device 有权
    刷新相变材料存储器件的存储单元

    公开(公告)号：US06768665B2

    公开(公告)日：2004-07-27

    申请号：US10212630

    申请日：2002-08-05

    申请人： Ward D. Parkinson ,  Tyler A. Lowrey

    发明人： Ward D. Parkinson ,  Tyler A. Lowrey

    IPC分类号： G11C1300

    CPC分类号： G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3418 ,  G11C16/3431 ,  G11C2013/0076 ,  G11C2013/0092

    摘要： Briefly, in accordance with an embodiment of the invention, an apparatus and method to provide refreshing of a memory cell of a phase change memory device is provided. The method includes determining whether a storage level of a phase change memory cell is within a predetermined margin from a resistance threshold. In response to the determination, the cell is selectively written. The apparatus includes a circuit to: determine whether a storage level of a phase change memory cell is within a predefined margin from a resistance threshold level; and in response to the determination, selectively write to the cell.

    摘要翻译： 简而言之，根据本发明的实施例，提供了一种用于提供相变存储器件的存储单元的刷新的装置和方法。 该方法包括确定相变存储单元的存储电平是否在与电阻阈值相关的预定余量内。 响应于确定，选择性地写入单元。 该装置包括：电路，用于：确定相变存储单元的存储电平是否处于来自电阻阈值电平的预定余量内; 并且响应于该确定，选择性地写入该单元。

    Pull up circuit for digit lines in a semiconductor memory
    2.
    发明授权
    Pull up circuit for digit lines in a semiconductor memory 失效
    上拉电路用于半导体存储器中的数字线

    公开(公告)号：US4924442A

    公开(公告)日：1990-05-08

    申请号：US252494

    申请日：1988-09-30

    申请人： Zhitong Chen ,  Gary M. Johnson ,  Ward D. Parkinson ,  Wen-Foo Chern ,  Tyler A. Lowrey ,  Thomas M. Trent

    发明人： Zhitong Chen ,  Gary M. Johnson ,  Ward D. Parkinson ,  Wen-Foo Chern ,  Tyler A. Lowrey ,  Thomas M. Trent

    IPC分类号： G11C11/4094

    CPC分类号： G11C11/4094

    摘要： A voltage sensing circuit is used to rapidly pull up a high potential node of a reference array to a value of a high potential source reduced by a threshold voltage (V.sub.CC -V.sub.T). During an enable cycle, the high potential node is precharged to a potential of V.sub.CC -V.sub.T, which turns on a transistor gated to the V.sub.CC potential. This pulls the high potential node as rapidly as possible to a high level in order to speed up the sensing process. A potential maintenance circuit provides sufficient current from the high potential source to maintain a desired potential at the high potential node.

    摘要翻译： 电压感测电路用于将参考阵列的高电位节点快速上拉至阈值电压（VCC-VT）降低的高电位源的值。 在使能周期期间，高电位节点被预充电到VCC-VT的电位，VCC-VT导通晶体管门控VCC电位。 这将高电位节点尽可能快地拉到高电平，以加速感测过程。 潜在维护电路提供来自高电位源的足够的电流以在高电位节点处保持期望的电位。

    Read bias scheme for phase change memories
    4.
    发明授权
    Read bias scheme for phase change memories 有权
    用于相变存储器的读偏置方案

    公开(公告)号：US07308067B2

    公开(公告)日：2007-12-11

    申请号：US10633872

    申请日：2003-08-04

    申请人： Tyler A. Lowrey ,  Ward D. Parkinson

    发明人： Tyler A. Lowrey ,  Ward D. Parkinson

    IPC分类号： G11C16/04

    CPC分类号： G11C13/004 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/76

    摘要： A read bias scheme may be used for phase change memories including a chalcogenide access device and a chalcogenide memory element. Through an appropriate read bias scheme, desirable read margin can be achieved. This may result in better yield, higher reliability, and ultimately lower costs in some cases.

    摘要翻译： 读偏置方案可用于包括硫族化物存取装置和硫族化物存储元件的相变存储器。 通过适当的读取偏置方案，可以实现理想的读取余量。 这可能导致更好的产量，更高的可靠性，并且在某些情况下最终降低成本。

    Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants
    7.
    发明授权
    Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants 失效
    分裂多晶硅CMOS工艺结合未屏蔽的穿透和源/漏植入

    公开(公告)号：US5032530A

    公开(公告)日：1991-07-16

    申请号：US427639

    申请日：1989-10-27

    申请人： Tyler A. Lowrey ,  Randal W. Chance ,  Ward D. Parkinson

    发明人： Tyler A. Lowrey ,  Randal W. Chance ,  Ward D. Parkinson

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/6659 ,  H01L21/823807

    摘要： An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly). The object of the improved process is to reduce the cost and improve the reliability and manufacturability of CMOS devices by dramatically reducing the number of photomasking steps required to fabricate transistors. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology. Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.

    摘要翻译： 一种改进的CMOS制造工艺，其使用单独的掩模步骤来从单层导电掺杂多晶硅（poly）中的N沟道和P沟道晶体管栅极图案化。 改进的过程的目的是通过显着减少制造晶体管所需的光掩模步骤的数量来降低成本并提高CMOS器件的可靠性和可制造性。 通过分别处理N沟道和P沟道器件，在单多晶硅层或单金属层工艺中制造完整的CMOS电路所需的光掩模步骤的数量可以从11减少到8个。 从P型材料的衬底开始，首先形成N沟道器件，在未来的P沟道区域中留下未蚀刻的聚合物，直到N沟道处理完成。 与传统工艺技术相比，改进的CMOS工艺提供了以下优点。 不需要对N沟道器件使用屏蔽的高能穿孔植入物; N通道和P沟道晶体管的单独优化成为可能; 容易实现用于N沟道和P沟道晶体管的轻掺杂漏极（LDD）设计; 源/漏 - 门偏移可以针对N沟道和P沟道器件独立地改变; 可以独立控制和优化N沟道和P沟道晶体管，以获得最佳的LDD性能和可靠性。

    Pull up circuit for sense lines in a semiconductor memory
    8.
    发明授权
    Pull up circuit for sense lines in a semiconductor memory 失效
    上拉电路用于半导体存储器中的感测线

    公开(公告)号：US4914631A

    公开(公告)日：1990-04-03

    申请号：US252585

    申请日：1988-09-30

    申请人： Gary M. Johnson ,  Zhitong Chen ,  Wen-Foo Chern ,  Ward D. Parkinson ,  Tyler A. Lowrey ,  Thomas M. Trent

    发明人： Gary M. Johnson ,  Zhitong Chen ,  Wen-Foo Chern ,  Ward D. Parkinson ,  Tyler A. Lowrey ,  Thomas M. Trent

    IPC分类号： G11C11/4094

    CPC分类号： G11C11/4094

    摘要： A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V.sub.CC -V.sub.T (where VT is a threshold voltage of a transistor).

    摘要翻译： 存储器阵列（例如，DRAM）设置有潜在的维护电路，其提供足够的电流以将存储器阵列的高电位节点保持在预定电位。 在接收到时钟信号并在预定电位门控OFF之后，潜在维护电路被选通。 这允许高压节点被维持，同时减少电流要求。 当与将快速将高节点上拉到VCC-VT（其中VT是晶体管的阈值电压）的电路结合使用时，本发明特别有用。

    Method and system to store information
    10.
    发明授权
    Method and system to store information 有权
    方法和系统来存储信息

    公开(公告)号：US06813177B2

    公开(公告)日：2004-11-02

    申请号：US10319756

    申请日：2002-12-13

    申请人： Tyler A. Lowrey ,  Ward D. Parkinson

    发明人： Tyler A. Lowrey ,  Ward D. Parkinson

    IPC分类号： G11C1100

    CPC分类号： G11C13/0004 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0092

    摘要： Briefly, in accordance with an embodiment of the invention, a method and system to program a memory material is provided. The method may include applying three signals having different durations and different amplitudes to a memory material to program the memory material to a predetermined state.

    摘要翻译： 简而言之，根据本发明的实施例，提供了一种用于对存储材料进行编程的方法和系统。 该方法可以包括将具有不同持续时间和不同幅度的三个信号应用于存储器材料以将存储器材料编程到预定状态。