利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

32 条记录 (耗时 0.022 秒)

    NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF
    1.
    发明申请
    NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF 有权
    非易失性存储器及其制造方法

    公开(公告)号：US20060110879A1

    公开(公告)日：2006-05-25

    申请号：US10904703

    申请日：2004-11-24

    申请人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

    发明人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of word lines is formed on the stack gate strips and the dielectric strips. Thereafter, the stack gate strips exposed by the word lines are removed to form a plurality of openings. A plurality of spacers is formed on the sidewalls of the openings and the word lines. A dielectric layer is formed over the substrate. A plurality of contacts is formed in the dielectric layer and the dielectric strips between two adjacent word lines.

    摘要翻译： 提供了一种制造非易失性存储器的方法。 在基板上形成多个堆叠栅极条，并且在堆叠栅极条旁边的基板中形成多个源极/漏极区域。 在源/漏区上形成多个介质条。 多个字线形成在堆叠栅极条和介质条上。 此后，除去由字线露出的堆叠栅极条以形成多个开口。 在开口和字线的侧壁上形成多个间隔物。 介电层形成在衬底上。 在电介质层和两个相邻字线之间的介质条形成多个触点。

    Method of forming a contact on a semiconductor device
    2.
    发明授权
    Method of forming a contact on a semiconductor device 有权
    在半导体器件上形成接触的方法

    公开(公告)号：US07776690B2

    公开(公告)日：2010-08-17

    申请号：US11691501

    申请日：2007-03-27

    申请人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

    发明人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.

    摘要翻译： 提供了一种在半导体器件上形成接触的方法。 首先，提供基板。 由第一方向上的多个字线限定的多个栅极结构和在第二方向上由第一电介质层覆盖的多个扩散区域设置在该基板上。 位于字线下方并由扩散区隔离的栅极结构。 然后，形成蚀刻停止层。 蚀刻停止层和第一介电层具有不同的蚀刻选择性。 第二介质层形成在衬底上。 此外，通过使用蚀刻停止层作为自对准掩模，形成到字线之间的扩散区域的多个接触孔。

    METHOD OF FORMING A CONTACT ON A SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF FORMING A CONTACT ON A SEMICONDUCTOR DEVICE 有权
    在半导体器件上形成接触的方法

    公开(公告)号：US20070190719A1

    公开(公告)日：2007-08-16

    申请号：US11691501

    申请日：2007-03-27

    申请人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

    发明人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.

    摘要翻译： 提供了一种在半导体器件上形成接触的方法。 首先，提供基板。 由第一方向上的多个字线限定的多个栅极结构和在第二方向上由第一电介质层覆盖的多个扩散区域设置在该基板上。 位于字线下方并由扩散区隔离的栅极结构。 然后，形成蚀刻停止层。 蚀刻停止层和第一介电层具有不同的蚀刻选择性。 第二介质层形成在衬底上。 此外，通过使用蚀刻停止层作为自对准掩模，形成到字线之间的扩散区域的多个接触孔。

    Non-volatile memory and fabricating method thereof
    4.
    发明授权
    Non-volatile memory and fabricating method thereof 有权
    非易失性存储器及其制造方法

    公开(公告)号：US07214983B2

    公开(公告)日：2007-05-08

    申请号：US10904703

    申请日：2004-11-24

    申请人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

    发明人： Tzung-Ting Han ,  Ming-Shang Chen ,  Wen-Pin Lu ,  Meng-Hsuan Weng

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of word lines is formed on the stack gate strips and the dielectric strips. Thereafter, the stack gate strips exposed by the word lines are removed to form a plurality of openings. A plurality of spacers is formed on the sidewalls of the openings and the word lines. A dielectric layer is formed over the substrate. A plurality of contacts is formed in the dielectric layer and the dielectric strips between two adjacent word lines.

    摘要翻译： 提供了一种制造非易失性存储器的方法。 在基板上形成多个堆叠栅极条，并且在堆叠栅极条旁边的基板上形成多个源极/漏极区域。 在源/漏区上形成多个介质条。 多个字线形成在堆叠栅极条和介质条上。 此后，除去由字线露出的堆叠栅极条以形成多个开口。 在开口和字线的侧壁上形成多个间隔物。 介电层形成在衬底上。 在电介质层和两个相邻字线之间的介质条形成多个触点。

    Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory
    5.
    发明授权
    Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory 有权
    非易失性存储单元及其制造方法以及制造非易失性存储器的方法

    公开(公告)号：US07271062B2

    公开(公告)日：2007-09-18

    申请号：US11223690

    申请日：2005-09-09

    申请人： Meng-Hsuan Weng ,  Tzung-Ting Han ,  Ming-Shang Chen

    发明人： Meng-Hsuan Weng ,  Tzung-Ting Han ,  Ming-Shang Chen

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

    摘要： A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls of the stack gate structures. After that, a plurality of conductive pad layers is formed on the exposed doped regions. By forming the conductive pad layers, the resistance of the doped region in each memory cell can be reduced.

    摘要翻译： 提供了一种制造非易失性存储器的方法。 在制造方法中，在衬底上形成多个堆叠栅极结构，并且在堆叠栅极结构旁边的衬底中形成多个掺杂区域。 然后，在堆叠栅极结构的侧壁上形成多个间隔物。 之后，在暴露的掺杂区域上形成多个导电焊盘层。 通过形成导电焊盘层，可以减小每个存储单元中的掺杂区域的电阻。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    9.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路装置及制造半导体集成电路装置的方法

    公开(公告)号：US20120119282A1

    公开(公告)日：2012-05-17

    申请号：US12945659

    申请日：2010-11-12

    申请人： Yu-Fong Huang ,  Tzung-Ting Han ,  Wen-Pin Lu

    发明人： Yu-Fong Huang ,  Tzung-Ting Han ,  Wen-Pin Lu

    IPC分类号： H01L27/11 ,  H01L21/336

    CPC分类号： H01L29/7926 ,  H01L27/11565 ,  H01L27/11582

    摘要： A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.

    摘要翻译： 用于半导体集成电路器件的系统，方法和布局允许改进可以包括触点和其它金属互连结构的各种后端结构的缩小。 所得到的结构可以包括半导体衬底，形成在半导体衬底上的掩埋扩散区，以及硅化物膜，例如硅化钨（WSix）和自对准硅化物（自对准硅）膜中的至少一种，例如钴 硅化物（CoSi）和/或硅化镍（NiSi），在掩埋扩散（BD）层之上。 半导体集成电路还可以包括形成在接触层的至少一部分上的存储器栅极结构。

    Semiconductor integrated circuit device and method of manufacturing a semiconductor integrated circuit device
    10.
    发明授权
    Semiconductor integrated circuit device and method of manufacturing a semiconductor integrated circuit device 有权
    半导体集成电路器件及半导体集成电路器件的制造方法

    公开(公告)号：US08466064B2

    公开(公告)日：2013-06-18

    申请号：US12945659

    申请日：2010-11-12

    申请人： Yu-Fong Huang ,  Tzung-Ting Han ,  Wen-Pin Lu

    发明人： Yu-Fong Huang ,  Tzung-Ting Han ,  Wen-Pin Lu

    IPC分类号： H01L21/44

    CPC分类号： H01L29/7926 ,  H01L27/11565 ,  H01L27/11582

    摘要： A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.

    摘要翻译： 用于半导体集成电路器件的系统，方法和布局允许改进可以包括触点和其它金属互连结构的各种后端结构的缩小。 所得到的结构可以包括半导体衬底，形成在半导体衬底上的掩埋扩散区，以及硅化物膜，例如硅化钨（WSix）和自对准硅化物（自对准硅）膜中的至少一种，例如钴 硅化物（CoSi）和/或硅化镍（NiSi），在掩埋扩散（BD）层之上。 半导体集成电路还可以包括形成在接触层的至少一部分上的存储器栅极结构。